Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Analysis of HW/SW On-Chip Communication in MP SOC Design 127
shared memory by a write operation (W1). Task T2 runs and writes its output
on its output physical buffer (W2). After task T3 completes its previous
computation at time t1, it reads from two input buffers (R1 and R2).
In Figure 10-1(c), we assume that the two edges of the task graph share
the same physical buffer to reduce the physical buffer overhead. In this case,
compared to the case of Figure 10-1(b), after the execution of task T2, the
task cannot write its output data on the shared physical buffer, since the shared
physical buffer is filled by task T1. Thus, the write operation of task T2 waits
until task T3 reads from its input buffer. When the shared physical buffer
becomes empty after the read of task T3, we assume that there is an interrupt
to task T2 to invoke its write operation (W2). Note that, in this case, the
dynamic behavior of SW architecture is not modeled. That is, the execution
delay of interrupt service routine and that of context switching are not modeled
in this case.
In Figure 10-1(d), the dynamic behavior of SW architecture is modeled.
Compared to the case of Figure 10-1(c), when the interrupt occurs to invoke
the write operation of task T2, first, it accounts for the execution delay of ISR.
Then, it accounts for the delay of context switching (CS). As this example
shows, compared to the case of Figure 10-1(c), when we model the dynamic
behavior of SW, we can obtain more accurate system runtime in scheduling
on-chip communication and task execution.