Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Analysis of HW/SW On-Chip Communication in MP SOC Design 129
boolean variable representing the state of node
constant boolean value representing the access type of communication
node
Communication delay is caused by both SW and HW communication architectures.
We decompose the delay into three parts as follows.
where n is the communication data size and and are
the delays of SW communication architecture, HW communication interface,
and on-chip communication network, respectively. The delay of software communication
architecture is given by
where is ISR delay, is CS delay and is device driver
delay. If the software task is running on a processor, ISR delay and CS delay
are zero. Else, the task is blocked and is in a wait state and the communication
interface interrupts the processor to wake up the task. Thus, the ISR and
CS delay should be counted into the communication time.