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Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

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Introduction to Hardware Abstraction Layers <strong>for</strong> SOC 185<br />

to validate the correct operation of reused SW in the HW architecture.<br />

However, since the <strong>de</strong>sign of HW architecture may not yet be finished, the<br />

HAL may not be <strong>de</strong>signed, either.<br />

In such a case, to enable the validation via simulation, we need a simulation<br />

mo<strong>de</strong>l of HAL. The simulation mo<strong>de</strong>l needs to simulate the functionality<br />

of HAL, i.e. context switch, interrupt processing, and processor I/O.<br />

The simulation mo<strong>de</strong>l of HAL can be used together with transaction level or<br />

RTL mo<strong>de</strong>ls of on-chip bus and other HW modules. The simulation mo<strong>de</strong>l<br />

needs also to support timing simulation of upper layer SW. More <strong>de</strong>tails of<br />

HAL simulation mo<strong>de</strong>l can be found in [7].<br />

5.2. Application-specific and automatic HAL <strong>de</strong>sign<br />

When a (standard) HAL API is generic (to support most of HW architectures)<br />

or plat<strong>for</strong>m-specific, it will provi<strong>de</strong> <strong>for</strong> good portability to upper layer<br />

SW. However, we can have a heavy HAL implementation (up to ~10 k lines<br />

of co<strong>de</strong> in the co<strong>de</strong> library [3]). In such a case, the HAL implementation may<br />

cause an overhead of system resource (in terms of co<strong>de</strong> size) and per<strong>for</strong>mance<br />

(execution <strong>de</strong>lay of HAL).<br />

To reduce such an overhead of HAL implementation, application-specific<br />

HAL <strong>de</strong>sign is nee<strong>de</strong>d. In this case, HAL needs to be tailored to the upper<br />

layer SW and HW architecture. To <strong>de</strong>sign such a HAL, we need to be able<br />

to implement only the HAL API functions (and their <strong>de</strong>pen<strong>de</strong>nt functions)<br />

used by the upper layer SW. To the best of our knowledge, there has been no<br />

research work to enable such an application-specific HAL <strong>de</strong>sign.<br />

Conventional HAL <strong>de</strong>sign is manually done <strong>for</strong> a give board, e.g. using a<br />

configuration tool such as Plat<strong>for</strong>m Buil<strong>de</strong>r <strong>for</strong> WindowCE. In the case of<br />

<strong>SoC</strong> <strong>de</strong>sign, we per<strong>for</strong>m <strong>de</strong>sign space exploration of HW architectures to<br />

obtain optimal HW architecture(s). For each of HW architecture candidates,<br />

HAL needs to be <strong>de</strong>signed. Due to the large number of HW architecture<br />

candidates, manual HAL <strong>de</strong>sign will be too time-consuming to enable fast

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