Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

360 Chapter 27
evaluate the performance improvement that can be achieved by exploiting
IR.
Dynamic Instruction Reuse (IR) [1, 2] improves the execution time of an
application by reducing the number of instructions that have to be executed
dynamically. Research has shown that many instructions are executed
repeatedly with the same inputs and hence producing the same output [3].
Dynamic instruction reuse is a scheme in which instructions are buffered in
a Reuse Buffer (RB) and future dynamic instances of the same instruction
use the results from the RB if they have the same input operands. The RB is
used to store the operand values and result of instructions that are executed
by the processor. This scheme is denoted by (‘v’ for value) and was
proposed by Sodani and Sohi [1]. The RB consists of tag, input operands,
result, address and memvalid fields [1]. When an instruction is decoded, its
operand values are compared with those stored in the RB. The PC of the
instruction is used to index into the RB. If a match occurs in the tag and
operand fields, the instruction under consideration is said to be reused and
the result from the RB is utilized i.e. the computation is not required. We
assume that the reuse test can be performed in parallel with instruction decode
[1] and register read stage. The reuse test will usually not lie in the critical
path since the accesses to the RB can be pipelined. The tag match can be
initiated during the instruction fetch stage since the PC value of an instruction
is known by then. The accesses into the operand fields in the RB can
begin only after the operand registers have been read (register read stage in
the pipeline). Execution of load instructions involves a memory address
computation followed by an access to the memory location specified by the
address. The address computation part of a load instruction can be reused if
the instruction operands match an entry in the RB, while the actual memory
value (outcome of load) can be reused if the addressed memory location was
not written by a store instruction [1]. The memvalid field indicates whether
the value loaded from memory is valid (i.e. has not been overwritten by store
instruction) while the address field indicates the memory address. When the
processor executes a store instruction, the address field of each RB entry is
searched for a matching address, and the memvalid bit is reset for matching
entries [1]. In this article we assume that the RB is updated by instructions
that have completed execution (non-speculative) and are ready to update the
register file. This ensures that precise state is maintained with the RB
containing only the results of committed instructions. IR improves performance
since reused instructions bypass some stages in the pipeline with the
result that it allows the dataflow limit to be exceeded. Performance improvement
depends on the number of pipeline stages between the register read and
writeback stages and is significant if long latency operations such as divide
instructions are reused. Additionally, in case of dynamically scheduled processors,
performance is further improved since subsequent instructions that are
dependent on the reused instruction are resolved earlier and can be issued
earlier (out-of-order issue).