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Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

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Chapter 30<br />

RAPID CONFIGURATION & INSTRUCTION<br />

SELECTION FOR AN ASIP: A CASE STUDY<br />

Newton Cheung 1 ‚ Jörg Henkel 2 and Sri Parameswaran 1<br />

1 School of Computer Science & Engineering‚ University of New South Wales‚ Sydney‚ NSW<br />

2052‚ Australia;<br />

2 NEC Laboratories America‚ 4 In<strong>de</strong>pen<strong>de</strong>nce Way‚ Princeton‚ NJ 08540‚<br />

USA<br />

Abstract. We present a methodology that maximizes the per<strong>for</strong>mance of Tensilica based<br />

Application Specific Instruction-set Processor (ASIP) through instruction selection when an area<br />

constraint is given. Our approach rapidly selects from a set of pre-fabricated coprocessors and<br />

a set of pre-<strong>de</strong>signed specific instructions from our library (to evaluate our technology we use<br />

the Tensilica plat<strong>for</strong>m). As a result‚ we significantly increase application per<strong>for</strong>mance while area<br />

constraints are satisfied. Our methodology uses a combination of simulation‚ estimation and a<br />

pre-characterised library of instructions‚ to select the appropriate coprocessors and instructions.<br />

We report that by selecting the appropriate coprocessors and specific instructions‚ the total<br />

execution time of complex applications (we study a voice enco<strong>de</strong>r/<strong>de</strong>co<strong>de</strong>r)‚ an application’s<br />

per<strong>for</strong>mance can be reduced by up to 85% compared to the base implementation. Our estimator<br />

used in the system takes typically less than a second to estimate‚ with an average error rate of<br />

4% (as compared to full simulation‚ which takes 45 minutes). The total selection process using<br />

our methodology takes 3–4 hours‚ while a full <strong>de</strong>sign space exploration using simulation would<br />

take several days.<br />

Key words: ASIP‚ Instruction selection‚ methodology<br />

1. INTRODUCTION<br />

<strong>Embed<strong>de</strong>d</strong> system <strong>de</strong>signers face <strong>de</strong>sign challenges such as reducing chip area‚<br />

increasing application per<strong>for</strong>mance‚ reducing power consumption and shortening<br />

time-to-market. Traditional approaches‚ such as employing general<br />

programmable processors or <strong>de</strong>signing Application Specific Integrated Circuits<br />

(ASICs)‚ do not necessarily meet all <strong>de</strong>sign challenges. While general programmable<br />

processors offer high programmability and lower <strong>de</strong>sign time‚ they<br />

may not satisfy area and per<strong>for</strong>mance challenges. On the other hand‚ ASICs<br />

are <strong>de</strong>signed <strong>for</strong> a specific application‚ where the area and per<strong>for</strong>mance can<br />

easily be optimised. However‚ the <strong>de</strong>sign process of ASICs is lengthy‚ and is<br />

not an i<strong>de</strong>al approach when time-to-market is short. In or<strong>de</strong>r to overcome the<br />

shortcomings of both general programmable processors and ASICs‚<br />

Application Specific Instruction-set Processors (ASIPs) have become popular<br />

in the last few years.<br />

ASIPs are <strong>de</strong>signed specifically <strong>for</strong> a particular application or a set of<br />

403<br />

A Jerraya et al. (eds.)‚ <strong>Embed<strong>de</strong>d</strong> <strong>Software</strong> <strong>for</strong> SOC‚ 403–417‚ 2003.<br />

© 2003 Kluwer Aca<strong>de</strong>mic Publishers. Printed in the Netherlands.

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