Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

98 Chapter 8
2. VISTA METHODOLOGY APPROACH
System level architects and application SW developers look for performance
analysis and overall behavior of the system. They do not necessarily need
and cannot make use of a cycle-accurate model of the SoC platform. However,
a pure un-timed C model is not satisfactory either since some timing notions
will still be required for performance analysis or power estimation. The capability
of VISTA to bring HW/SW SoC modeling and characterization to the
fore is key as it is shown in Figure 8-1.
VISTA can be decomposed into at least two major use paradigms:
1.
2.
Creation of the SoC virtual platform for system analysis and architecture
exploration.
Use of the SoC virtual platform for SW development and system analysis
by the systems houses SW or system designers.
Before system performance analysis, the designer has to leverage the
existing HW library delivered with VISTA library to create the appropriate
SoC platform architecture. The generic VISTA elements delivered in the
library include: Bus (STBus, AHB/APB), Memories, Peripherals (timers,
DMA, IOs, etc.) and RTOS elements.
Using the provided virtual model of the SoC, including the hardware
abstraction layer and the RTOS layer, system designers and application SW
designers can use VISTA to simulate and analyze system performance in terms