Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Exploring SW Performance 109
modem or its buffer size. One may also maintain a an observable Boolean
variable, true as long as a percentile of missed frame occurs.
4. CONCLUSION
We have presented a new methodology and tool for modeling SoC virtual
platform for SW development and system level performance analysis and
exploration. Using our VISTA methodology approach, we have been able to
simulate the performances of a limited Visio phone system by generating
10,000 bus transactions per second, and running 0.5 second real time
simulation in 20s while having the traces activated.
This environment is not primary intended for debugging a system. Some
defects may be rather difficult to be shown with the tool, and the assertions
may hardly be used for other purposes than performance and parallelism
analysis due to the computational model.
But we think that such a level of modelling can allow to extract a formal
specification of the system, if the communication channels are previously formalized
[8, 9].
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