Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

Data Space Oriented Scheduling 243
one that will reuse the cache contents most). Method3 does not restructure
the process codes and but tries to reorder their schedule order to minimize
cache conflicts. Method4 is similar to the original (default) scheme except that
the arrays are placed in memory so as to minimize the conflict misses. To
obtain this version, we used extensive array padding. We see from these results
that our strategy outperforms the remaining scheduling strategies for all benchmarks
in our experimental suite. The reason for this is that in many cases it
is not sufficient to just try to reuse the contents of the cache by considering
the previously-scheduled process.
4. CONCLUDING REMARKS
Process scheduling is a key issue in any multi-programmed system. We present
a locality conscious scheduling strategy whose aim is to exploit data cache
locality as much as possible. It achieves this by restructuring the process codes
based on data sharing between processes. Our experimental results indicate
that the scheduling strategy proposed brings significant performance benefits.
NOTE
1 A reference to an array can be represented by where is a linear transformation
matrix called the array reference (access) matrix, is the offset (constant) vector; is a column
vector, called iteration vector, whose elements written left to right represent the loop indices
starting from the outermost loop to the innermost in the loop nest.
REFERENCES
l. S. P. Amarasinghe, J. M. Anderson, M. S. Lam, and C. W. Tseng. “The SUIF Compiler for
Scalable Parallel Machines.” In Proceedings of the 7th S1AM Conference on Parallel
Processing for Scientific Computing, February, 1995.
2. W. Kelly, V. Maslov, W. Pugh, E. Rosser, T. Shpeisman, and David Wonnacott. “The Omega
Library Interface Guide.” Technical Report CS-TR-3445, CS Department, University of
Maryland, College Park, MD, March 1995.
3. I. Kodukula, N. Ahmed, and K. Pingali. “Data-Centric Multi-Level Blocking.” In Proceedings
of ACM SIGPLAN Conference on Programming Language Design and Implementation, June
1997.
4. C-G. Lee et al. “Analysis of Cache Related Preemption Delay in Fixed-Priority Preemptive
Scheduling.” IEEE Transactions on Computers, Vol. 47, No. 6, June 1998.
5. Y. Li and W. Wolfe. “A Task-Level Hierarchical Memory Model for System Synthesis of
Multiprocessors.” IEEE Transactions on CAD, Vol. 18, No, 10, pp. 1405-1417, October 1999.
6. WARTS: Wisconsin Architectural Research Tool Set. http://www.cs.wisc.edu/~larus/
warts.html
7. W. Wolfe. Computers as Components: Principles of Embedded Computing System Design,
Morgan Kaufmann Publishers, 2001.
8. A. Wolfe. “Software-Based Cache Partitioning for Real-Time Applications.” In Proceedings
of the Third International Workshop on Responsive Computer Systems, September 1993.