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Embedded Software for SoC - Grupo de Mecatrônica EESC/USP

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In<strong>de</strong>x 529<br />

packet flows<br />

parameter passing<br />

pareto points<br />

partitioning<br />

per<strong>for</strong>mance analysis<br />

per<strong>for</strong>mance constraint<br />

per<strong>for</strong>mance estimation<br />

peripheral <strong>de</strong>vice mo<strong>de</strong>ling<br />

petri nets<br />

physical layer<br />

picture-in-picture (PIP)<br />

pipeline<br />

pipeline latches<br />

pipelined cache<br />

pipeline stall<br />

plat<strong>for</strong>m in<strong>de</strong>pen<strong>de</strong>nce<br />

plat<strong>for</strong>m-based HW/SW co-<strong>de</strong>sign<br />

polytope<br />

posix threads<br />

porting<br />

power estimation<br />

predication<br />

process<br />

process scheduling<br />

product line<br />

programming languages<br />

protected OS<br />

quantitative constraint<br />

quasi-static scheduling<br />

rabbit<br />

reachability graph<br />

reactive systems<br />

real time operating systems (RTOS)<br />

real-time<br />

real-time systems<br />

region <strong>de</strong>tection<br />

reliability mo<strong>de</strong>l<br />

Rijndael<br />

RMC2000<br />

resource conflict<br />

RTOS<br />

RTOS characterization<br />

RTOS mo<strong>de</strong>l/mo<strong>de</strong>ling and abstraction<br />

RTOS mo<strong>de</strong>ling<br />

runtime optimization<br />

safety critical<br />

safety-critical system<br />

Satisfiability<br />

schedulability analysis<br />

scheduling analysis<br />

sdram<br />

selfishness<br />

Sequence-Loss<br />

SET<br />

SEU<br />

SIMD Reconfigurable architecture<br />

SimpleScalar<br />

simulation<br />

simulation mo<strong>de</strong>l of HAL<br />

simulation monitor<br />

simulation speedup<br />

simulation verification<br />

simultaneous multithreading<br />

<strong>SoC</strong><br />

sockets<br />

software engineering<br />

software generation<br />

software integration<br />

software per<strong>for</strong>mance validation<br />

software synthesis<br />

software-<strong>de</strong>tection<br />

source co<strong>de</strong> trans<strong>for</strong>mation<br />

speculation<br />

speech recognition<br />

specification methodology<br />

static/dynamic energy<br />

stochastic communication<br />

synchronization Errors<br />

system-level <strong>de</strong>sign<br />

system-level <strong>de</strong>sign language (SLDL)<br />

(system-level) <strong>de</strong>sign methodology<br />

system-level mo<strong>de</strong>ling<br />

System-on-Chip<br />

System on Chip Bus<br />

SystemC<br />

SWCD<br />

system-on-a-chip<br />

software integration<br />

<strong>Software</strong> Architectural Trans<strong>for</strong>mations<br />

<strong>Software</strong> Streaming<br />

<strong>SoC</strong><br />

software reuse<br />

State space compression<br />

<strong>Software</strong> synthesis<br />

task management<br />

task migration<br />

task synchronization & communication<br />

TCP<br />

thread<br />

time-sharing<br />

time-triggered architecture<br />

time/<strong>de</strong>lay mo<strong>de</strong>ling<br />

timing back-annotation<br />

transaction Level Mo<strong>de</strong>ling TLM

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