Radio Frequency Integrated Circuit Design - Webs

LNA Design
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inductor is increased, the impedance will (at some point) have a real
part equal to 50�.
4. The last step in the matching is simply to place an inductor in series
with the base L b . Without this inductor, the input impedance is
capacitive due to C� . This inductor is sized so that it resonates with
L e and C� at the center frequency of the design. This makes the
resultant input impedance equal to 50� with no additional reactive
component.
The technique above has several advantages over other matching techniques.
It is simple and requires only one additional matching component in
series with the input of the transistor. It produces a relatively broadband match
and it achieves simultaneous noise and power matching of the transistor. This
makes it a preferred method of matching.
There are many instances where this method cannot be applied without
modification. For some designs, power constraints may not accommodate the
necessary current to achieve the best noise performance. In this case, the design
could proceed as before, except with a less than optimum current density. In
other cases, the design may not provide the necessary gain required for some
applications. In this case, more current may be needed or some other matching
technique that does not require degeneration may have to be employed. Also,
linearity constraints may demand a larger amount of degeneration than this
method would produce.
Example 6.10 Simultaneous Noise and Power Matching
Design an LNA to work at 5 GHz using a 1.8-V supply with the simultaneous
noise and power matching technique discussed in this chapter. For the purpose
of this example, design a simple buffer so that the circuit can drive 50�. Assume
that a 50-GHz 0.5-�m SiGe technology is available.
Solution
At 1.8V it is still possible to design an LNA using a cascode configuration. The
cascode transistor can have its base tied to the supply. A simple output buffer
that will drive 50� quite nicely is an emitter follower. Thus, the circuit would
be configured as shown in Figure 6.17. In this case, V bias will be set to 1.8V.
The buffer should be designed to accommodate the linearity required by the
circuit and drive 50�, but for the purposes of this example, we will set the
current I bias at 3 mA. This will mean that the output impedance of the circuit
will be roughly 8.3� and there will be very little voltage loss through the
follower. Note that in industry common-emitter buffers are often used to
drive off-chip loads at this frequency for reasons of stability and short-circuit
protection. However, if the LNA drives an on-chip mixer, this should be fine.