Radio Frequency Integrated Circuit Design - Webs

Voltage-Controlled Oscillators
Loop gain = 40 dB = 20 log (10 � 399 � A 2)
A 2 = 25.1 mA
V
Thus, from (8.109) we can size the limiting transistors to give the required
gain:
A 2 =
Vtank IS e 2vT √�vTVtank
2�
Vtank e 2vT IS = A
√�vTVtank
− I Vtank S e 2vT √ �
V
vT 3/2
tank
−
Vtank e 2vT √ �
V
vT 3/2
tank�−1
= 2.51 mA
1.7V
�
e 2(25 mV)
V
√�(25 mV)(1.7V) −
= 1.59 × 10 −17 A
1.7V
e 2(25 mV)
25 mV 1.7V3/2�−1
√ �
This sets the size of these transistors to be 15.9 �m, which is a reasonable
size and will likely not load the resonator very much.
Now we can find the pole in the oscillator.
It is located at
f 2 = � 2
2� =
1
2�Rp C var
=
1
= 100.1 MHz
2�(628.3�)(2.53 pF)
This means that at 1 GHz, this pole will provide 20 dB of attenuation
from the dc value. Thus, the other pole will likewise need to provide 20 dB of
attenuation and must also be located at 100 MHz. Since this will lead to both
poles being at the same frequency, this design will end up with poor phase
margin. We will finish the example as is and fix the design in the next example.
The other pole is located at
f 1 = �1
2� = g m5
2�C ⇒ C = g m5
=
2�f 1
(10.34 mS)
= 16.45 pF
2�(100 MHz)
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