Radio Frequency Integrated Circuit Design - Webs

168 Radio Frequency Integrated Circuit Design
Figure 6.20 Plot showing the input matching for the LNA.
The gain is plotted in Figure 6.21. Note that it peaks about 400 MHz
lower than initially calculated. This is due to the capacitance of the transistor
Q 2 and the output buffer transistor Q 3. This could be adjusted by reducing
the capacitor C T until the gain is once more centered properly. The gain should
have a peak value given by (6.34), which in this case would have a value of
| vout
v in | = R L�T
R S �o
= 314� (2 � � � 39.4 GHz)
50� (2 � � � 5 GHz)
= 33.9 dB
minus the loss in the buffer. The gain was simulated to have a peak value of
about 29 dB, which is close to this value. If this gain is found to be too high,
it can be reduced by reducing L T or adding resistance to the resonator.
Figure 6.21 Plot showing the gain of the LNA.