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Radio Frequency Integrated Circuit Design - Webs

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I C_AVE = 1<br />

Voltage-Controlled Oscillators<br />

2� � 2�<br />

0<br />

I S e<br />

307<br />

Vtank sin (� )<br />

2vT d� = IS IO�Vtank 2v � (8.107)<br />

T<br />

where IO (x) is a modified Bessel function of the first kind of order zero, and<br />

IS is the saturation current. For fairly large V tank/2v T , there is an approximate<br />

solution:<br />

IC_AVE ≈ I Vtank S � e 2vT √<br />

Vtank<br />

2�<br />

2vT (8.108)<br />

Now we can write the gain of this part of the loop, which is a nonlinear<br />

function of V tank (all other parts of the loop were described by linear functions):<br />

A 3(s) = 2 ∂I C_AVE<br />

∂V tank<br />

= I Vtank S � e 2vT −<br />

√�vTVtank<br />

I Vtank S � e 2vT √ �<br />

V<br />

VT 3/2<br />

tank<br />

(8.109)<br />

Here it is assumed that this part of the loop has poles at a significantly<br />

higher frequency than the one in the VCO and the one in the mirror.<br />

These equations can be used to design the loop and demonstrate the<br />

stability of this circuit. The capacitor C 2 is placed in the circuit to create a<br />

dominant and controllable pole P1 significantly below the other pole P2. Generally,<br />

the frequency of P2 and gain of A 2(s) are set by the oscillator requirements<br />

and are not adjustable. For more stability, the loop gain can be adjusted by<br />

either changing the gain in A 1(s) (by adjusting the ratio of the current mirror)<br />

or by adjusting the gain of A 3(s) (this can be done by changing the size of the<br />

limiting transistors Q 3 and Q 4). Reducing the gain of the loop is a less desirable<br />

alternative than adjusting P1, because as the loop gain is reduced, its ability to<br />

settle to an exact final value is reduced.<br />

Example 8.11 The <strong>Design</strong> of a VCO AAC Loop<br />

<strong>Design</strong> an AAC loop for the VCO schematic shown in Figure 8.47. Use L =<br />

5nH(Q = 10), VCC = 5V. The AAC loop should be set up so that the dc<br />

gain around the loop is 40 dB to ensure that the final dc current through the<br />

oscillator is set accurately. The loop is to have 0-dB gain at 1 GHz to ensure<br />

that parasitic phase shift has minimal impact on the stability of the design.<br />

Also, find the phase margin of the loop. Assume that Js = 1 × 10 −18 A/�m<br />

and � = 100 in this technology. Use no more than a gain of 1:10 in the current<br />

mirror.

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