Radio Frequency Integrated Circuit Design - Webs

Power Amplifiers
B = 0.1836 0.81Q
R �1 +
Q 2 + 4�
Q ≈ � 0L
R
373
(10.28)
(10.29)
Then we may need to insert a filter between C o and R to prevent excessive
harmonic currents from reaching R.
10.7.4 Saturation Voltage and Resistance
Previously it was assumed that the output voltage would be zero when the
transistor was on. In reality, it will be equal to the transistor saturation voltage
V SAT. As described in [4], this can be accounted for by replacing the power
supply voltage with V eff = VCC − V SAT for all calculations, except power input.
As for the transistor having nonzero on resistance R on, this can be accounted
for by changing the value of V eff by V eff ≈ R/(R + 1.365R on)V CC . This is
valid for a 50% duty cycle.
10.7.5 Transition Time
Ideally, no power is dissipated during the transition between off and on. The
turn-on transition for nonoptimum conditions can be approximated with a
linear ramp of current. This produces a parabolic collector voltage waveform.
As described in [4], the current and voltage waveforms can be integrated to
determine dissipated power PdT .
PdT = 1 2
�
12 S Po
(10.30)
where �S is the transition time in radians and Po is the output power. Then
efficiency is given by
� = 1 − 1
12 � S
(10.31)
The above losses due to saturation voltage on resistance and turn-on
transient can be combined by summing dissipated power or by finding each
efficiency by itself and then multiplying the efficiencies.
Further information and detailed examples of class E amplifier designs
are shown by Cripps [5] and by Albulet [6].