Radio Frequency Integrated Circuit Design - Webs

Voltage-Controlled Oscillators
frequency (say, 3 GHz), but then the second harmonic would not be attenuated
by the loop, which could lead to other problems.
Note that the gain and amount of pole separation are still not enough to
make the design practical. If we were designing a product, we would continue
to refine these values until we are sure that the feedback loop will not oscillate
under any conditions.
We again employ a math tool to plot the frequency response of the
equations.
From the plot in Figure 8.50 we can see that there is now about 16° of
phase margin, which is still not great, but safer than the original design. Instead
of trying to refine the design, let us simply perform some initial simulations to
demonstrate the operation of the circuit.
The supply was chosen to be 5V, the base was biased at 2.5V, and the
reference current was chosen as 300 �A. The results are plotted in Figure 8.51,
which shows the base and collector waveforms of Q 1 or Q 2. Note that the
collector voltage is always higher than the base voltage, ensuring that the transistor
never saturates.
Figure 8.52 shows the current in transistor Q 6. Note that we have started
the reference current at almost 8 mA. Once the loop begins to operate, it brings
this current back to a value necessary to give the designed amplitude. This is
about 4.5 mA. Note that this is higher than the estimated current. This is
because the resonator voltage is higher than we estimated at the start of the
example, and thus more current is required. Figure 8.53 shows the response of
the first design biased under similar conditions. Note that with the poles at the
same frequency, the response is much less damped. One would expect that in
Figure 8.50 Gain and phase response of the improved AAC loop.
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