Radio Frequency Integrated Circuit Design - Webs

Power Amplifiers
stabilization. Then input power was swept to determine the power level at
which the current went to zero. This power was used as a starting point for
several iterations of sweeps of load pull and input power used to determine the
optimal output load and the required input power. The transistor current crosses
zero for an input power of about 8 dBm, as shown in Figure 10.18. The load
pull shown in Figure 10.19 indicated the optimal load should be 9 + j7.6. This
is a little bit lower than the predicted 15.6�, explained largely by the reduced
voltage swing compared to that predicted. The inductive portion of the load
( j7.6) accounts largely for the transistor output capacitance. The sweeps of
Pout and power-added efficiency versus P in shown in Figure 10.20 shows that
1-dB compression occurs at an input power of about 9 or 10 dBm and that
power-added efficiency is just over 30% at an input power of 8 dBm, rising to
about 42% at 10 dBm. The output power is about 23 dBm as required.
Several differences can be seen between this simulation and simple theory.
The simple equations were derived assuming that output voltage swings from
0 to 6V. This does not happen, and thus power is a little bit low. This also
directly leads to a lower optimal load impedance than was initially calculated.
In this example, ideal models were used for passives and packaging. Obviously,
realistic models would have resulted in a reduction in efficiency.
Figure 10.18 Voltage and current waveforms for input power levels of 8, 9, and 10 dBm.
365