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Radio Frequency Integrated Circuit Design - Webs

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R E = re� v IP3<br />

2vT� 2/3<br />

LNA <strong>Design</strong><br />

546 mV<br />

− re = 5��2 � 25 mV� 2/3<br />

− 5� = 19.6�<br />

This is a rough estimate for what the linearity should be. Also, there are<br />

many other factors that can limit the linearity of the circuit. We will start with<br />

R E = 20�.<br />

The gain can also be found now. Knowing that we want 12 dB of voltage<br />

gain means a gain of 4 V/V. We will assume that the buffer has a voltage gain<br />

A BO of about 0.9 (they will always have a bit of loss). Thus, the load resistance<br />

can be obtained:<br />

G =<br />

R L<br />

A<br />

R E + re<br />

BO ⇒ R L = G<br />

(R<br />

A E + re ) =<br />

BO<br />

4<br />

(20� + 5�) ≈ 115�<br />

0.9<br />

Now we need to set the feedback resistor. Knowing that the input impedance<br />

needs to be 75� (we approximate that the input impedance is R f divided<br />

by the gain),<br />

Z in ≈<br />

R f<br />

R L<br />

R E + re<br />

⇒ R f = Z inRL<br />

R E + r e<br />

= 75� �115�<br />

20� + 5�<br />

= 345�<br />

The other thing that must be set is the value of C f . Since the LNA must<br />

operate down to 50 MHz, this capacitor will have to be fairly large. At 50<br />

MHz, if it has an impedance that is 1/20th of R f , then this would make it<br />

approximately 50 pF. We will start with this value. It can be refined in simulation<br />

later.<br />

The only thing left to do in this example is to size the transistors. With<br />

all the feedback around this design, the transistors will have a much smaller<br />

bearing on the noise figure than in a tuned LNA. Thus, we will make the input<br />

transistor fairly large (60 �m) and the other two transistors will be sized to be<br />

30 �m fairly arbitrarily. Having high f T is important, but in a 50-GHz process,<br />

this will probably not be an issue. The other last detail that needs to be addressed<br />

is the bias level at the base of Q 2. Given that the emitter of Q 1 is at 100 mV,<br />

the base will have to sit at about 1V. The collector of Q 1 should be higher<br />

than this, for example, about 1.2V. This means that the base of Q 2 will need<br />

to be at about 2.2V, and since its collector will sit at about 2.7V, this transistor<br />

will have plenty of headroom.<br />

The noise figure of this design can now be estimated. First, the noise<br />

voltage produced by the source resistance is<br />

191

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