Digital Electronics: Principles, Devices and Applications

128 Digital Electronics4K 1301.6KVCCInputAQ1Q3 D 2Q2Output YD 11KQ4GNDFigure 5.8Inverter in the standard TTL.VCC4K 1.6K 130InputA4KQ 5D3OutputYQ 1Q 3GNDD 1D2InputBQ 2Q41KQ6Figure 5.9NOR gate in the standard TTL.remain in cut-off, thus driving Q 6 to cut-off and Q 5 to conduction, is the one when both the inputsare in the logic LOW state. The output in such a case is logic HIGH. For all other input conditions,either Q 3 or Q 4 will conduct, driving Q 6 to saturation and Q 5 to cut-off, producing a logic LOW atthe output.5.3.2.3 AND GateFigure 5.10 shows the internal schematic of an AND gate in the standard TTL family. The schematicshown is that of one of the four AND gates in a quad two-input AND gate (type 7408/5408). In orderto explain how this schematic arrangement behaves as an AND gate, we will begin by investigatingthe input condition that would lead to a HIGH output. A HIGH output implies Q 6 to be in cut-off andQ 5 to be in conduction. This can happen only when Q 4 is in cut-off. Transistor Q 4 can be in the cut-off