Digital Electronics: Principles, Devices and Applications

154 Digital ElectronicsVDDAQ1BQ 2Y=(A+B)Q 3Q4Figure 5.37Two-input NOR in CMOS.input combinations, either of the two parallel N-channel devices will be conducting and either of thetwo series-connected P-channel devices will be nonconducting. We have either Q 1 OFF and Q 3 ONor Q 2 OFF and Q 4 ON. The output in both cases is logic ‘0’, which verifies the remaining entries ofthe truth table.Figure 5.38 shows how the circuit of Fig. 5.37 can be extended to build a three-input NOR gate.The operation of this circuit can be explained on similar lines. As already explained, NOR gates withmore than three inputs are usually realized as a combination of simpler gates.5.5.1.4 AND GateAn AND gate is nothing but a NAND gate followed by an inverter. Figure 5.39 shows the internalschematic of a two-input AND in CMOS. A buffered AND gate is fabricated by using a NOR gateschematic with inverters at both of its inputs and its output feeding two series-connected inverters.5.5.1.5 OR GateAn OR gate is nothing but a NOR gate followed by an inverter. Figure 5.40 shows the internalschematic of a two-input OR in CMOS. A buffered OR gate is fabricated by using a NAND gateschematic with inverters at both of its inputs and its output feeding two series-connected inverters.5.5.1.6 EXCLUSIVE-OR GateAn EXCLUSIVE-OR gate is implemented using the logic diagram of Fig. 5.41(a). As is evident fromthe figure, the output of this logic arrangement can be expressed byA + B+ AB = AB + AB = EX − OR function (5.1)