Digital Electronics: Principles, Devices and Applications

280 Digital Electronics8.1.4 Cascading Multiplexer CircuitsThere can possibly be a situation where the desired number of input channels is not available in ICmultiplexers. A multiple number of devices of a given size can be used to construct multiplexers thatcan handle a larger number of input channels. For instance, 8-to-1 multiplexers can be used to construct16-to-1 or 32-to-1 or even larger multiplexer circuits. The basic steps to be followed to carry out thedesign are as follows:1. If 2 n is the number of input lines in the available multiplexer and 2 N is the number of input lines inthe desired multiplexer, then the number of individual multiplexers required to construct the desiredmultiplexer circuit would be 2 N −n .2. From the knowledge of the number of selection inputs of the available multiplexer and that of thedesired multiplexer, connect the less significant bits of the selection inputs of the desired multiplexerto the selection inputs of the available multiplexer.3. The left-over bits of the selection inputs of the desired multiplexer circuit are used to enable ordisable the individual multiplexers so that their outputs when ORed produce the final output. Theprocedure is illustrated in solved example 8.3.Example 8.3Design a 16-to-1 multiplexer using two 8-to-1 multiplexers having an active LOW ENABLE input.SolutionA 16-to-1 multiplexer can be constructed from two 8-to-1 multiplexers having an ENABLEinput. The ENABLE input is taken as the fourth selection variable occupying the MSB position.Figure 8.14 shows the complete logic circuit diagram. IC 74151 can be used to implement an 8-to-1multiplexer.The circuit functions as follows. When S 3 is in logic ‘0’ state, the upper multiplexer is enabled andthe lower multiplexer is disabled. If we recall the truth table of a four-variable Boolean function, S 3would be ‘0’ for the first eight entries and ‘1’ for the remaining eight entries. Therefore, when S 3 = 0the final output will be any of the inputs from D 0 to D 7 , depending upon the logic status of S 2 , S 1 andS 0 . Similarly, when S 3 = 1 the final output will be any of the inputs from D 8 to D 15 , again dependingupon the logic status of S 2 , S 1 and S 0 . The circuit therefore implements the truth table of a 16-to-1multiplexer.8.2 EncodersAn encoder is a multiplexer without its single output line. It is a combinational logic function that has2 n (or fewer) input lines and n output lines, which correspond to n selection lines in a multiplexer.The n output lines generate the binary code for the possible 2 n input lines. Let us take the case of anoctal-to-binary encoder. Such an encoder would have eight input lines, each representing an octal digit,and three output lines representing the three-bit binary equivalent. The truth table of such an encoderis given in Table 8.8. In the truth table, D 0 to D 7 represent octal digits 0 to 7. A, B and C representthe binary digits.