Digital Electronics: Principles, Devices and Applications

Computer Fundamentals 615DataInputInputBuffersR/WA 5A 401Register '0'Register '1'AddressInputsA 3A 26-Lineto64-LineDecoderCSA 1A 063Register '63'OutputBuffersData OutputFigure 15.6Typical architecture of a 64×8 asynchronous SRAM.The different timing intervals shown in the diagram are defined as follows:• Complete read cycle time t RC . This is defined as the time interval for which a valid address code isapplied to the address lines during the ‘read’ operation.• RAM access time t ACC . This is defined as the time lapse between the application of a new addressinput and the appearance of valid output data.• Chip enable access time t CO . This is defined as the time taken by the RAM output to go from theHi-Z state to a valid data level once CS is activated.• Chip disable access time t OD . This is defined as the time taken by the RAM to return to the Hi-Zstate after CS is deactivated.