Digital Electronics: Principles, Devices and Applications

384 Digital ElectronicsSQClkFFR—Q(a)SQClkFFR—Q(b)Figure 10.25 (a) Circuit symbol of a positive edge-triggered R-S flip-flop and (b) the circuit symbol of a negativeedge-triggered R-S flip-flop.and not the pulse width of the input clock signal. This phenomenon is referred to as the raceproblem. As the propagation delays are normally very small, the likelihood of the occurrence ofa race condition is reasonably high. One way to get over this problem is to use a master–slaveconfiguration. Figure 10.30(a) shows a master–slave flip-flop constructed with two J-K flip-flops.The first flip-flop is called the master flip-flop and the second is called the slave. The clock tothe slave flip-flop is the complement of the clock to the master flip-flop. When the clock pulseis present, the master flip-flop is enabled while the slave flip-flop is disabled. As a result, themaster flip-flop can change state while the slave flip-flop cannot. When the clock goes LOW, themaster flip-flop gets disabled while the slave flip-flop is enabled. Therefore, the slave J-K flip-flopchanges state as per the logic states at its J and K inputs. The contents of the master flip-flopare therefore transferred to the slave flip-flop, and the master flip-flop, being disabled, can acquirenew inputs without affecting the output. As would be clear from the description above, a master–slave flip-flop is a pulse-triggered flip-flop and not an edge-triggered one. Figure 10.30(b) showsthe truth table of a master–slave J-K flip-flop with active LOW PRESET and CLEAR inputs andactive HIGH J and K inputs. The master–slave configuration has become obsolete. The newer ICtechnologies such as 74LS, 74AS, 74ALS, 74HC and 74HCT do not have master–slave flip-flops in theirseries.