Digital Electronics: Principles, Devices and Applications

Logic Families 1315.3.2.6 AND-OR-INVERT GateFigure 5.13 shows the internal schematic of a two-wide, two-input AND-OR-INVERT or AND-NORgate. The schematic shown is that of one of the two gates in a dual two-wide, two-input AND-OR-INVERT gate (type 7450/5450). The two multi-emitter input transistors Q 1 and Q 2 provide ANDingof their respective inputs. Drive splitters comprising Q 3 , Q 4 , R 3 and R 4 provide the OR function. Theoutput stage provides inversion. The number of emitters in each of the input transistors determines thenumber of literals in each of the minterms in the output sum-of-products Boolean expression. Howwide the gate is going to be is decided by the number of input transistors, which also equals the numberof drive splitter transistors.5.3.2.7 Open Collector GateAn open collector gate in TTL is one that is without a totem-pole output stage. The output stage inthis case does not have the active pull-up transistor. An external pull-up resistor needs to be connectedfrom the open collector terminal of the pull-down transistor to the V CC terminal. The pull-up resistoris typically 10 k. Figure 5.14 shows the internal schematic of a NAND gate with an open collectoroutput. The schematic shown is that of one of the four gates of a quad two-input NAND (type74/5401). The advantage of open collector outputs is that the outputs of different gates can be wiredtogether, resulting in ANDing of their outputs. WIRE-AND operation was discussed in Chapter 4 onlogic gates.It may be mentioned here that the outputs of totem-pole TTL devices cannot be tied together.Although a common tied output may end up producing an ANDing of individual outputs, such aconnection is impractical. This is illustrated in Fig. 5.15, where outputs of two totem-pole output TTLInput AInput BD 1VCCR1R3 R54K1.6K 130Q1Q3D 2R 24KQ 4Input CInput DD3D 4Q2Q5Q6D5Output Y1X1X(Not on Gate 2)R 41KGNDFigure 5.13Two-input, two-wide AND-OR-INVERT gate.