Digital Electronics: Principles, Devices and Applications

142 Digital ElectronicsFigure 5.24Handling unused inputs of AND and NAND gates.OR and NOR gates, which do not use a multi-emitter input transistor and use separate input transistorsinstead, as shown in Fig. 5.28. In this case, the input loading is n times the loading of a single inputfor both HIGH and LOW states.5.3.11 Current Transients and Power Supply DecouplingTTL family devices are prone to occurrence of narrow-width current spikes on the power supply line.Current transients are produced when the totem-pole output stage of the device undergoes a transitionfrom a logic LOW to a logic HIGH state. The problem becomes severe when in a digital circuit alarge number of gates are likely to switch states at the same time. These current spikes produce voltagespikes due to any stray inductance present on the line. On account of the large rate of change in currentin the current spike, even a small value of stray inductance produces voltage spikes large enoughadversely to affect the circuit performance.Figure 5.29 illustrates the phenomenon. When the output changes from LOW to HIGH, there isa small fraction of time when both the transistors are conducting because the pull-up transistor Q 3has switched on and the pull-down transistor Q 4 has not yet come out of saturation. During thissmall fraction of time, there is an increase in current drawn from the supply; I CCL experiences apositive spike before it settles down to a usually lower I CCH . The presence of any stray capacitanceC across the output owing to any stray wiring capacitance or capacitance loading of the circuit beingfed also adds to the problem. The problem of voltage spikes on the power supply line is usuallyovercome by connecting small-value, low-inductance, high-frequency capacitors between V CC terminaland ground. It is standard practice to use a 0.01 or 0.1 F ceramic capacitor from V CC to ground. This