Digital Electronics: Principles, Devices and Applications

Computer Fundamentals 619as in the case of an asynchronous SRAM. As mentioned before, most synchronous SRAMs have anaddress burst feature. In this case, when an external address is latched to the address register, a certainnumber of lowest address bits are applied to the burst logic. Burst logic comprises a binary counterand EXCLUSIVE-OR gates. The output of the burst logic, which basically produces a sequence ofinternal addresses, is fed to the address bus decoder. In the case of a two-bit burst logic, the internaladdress sequence generated is given by A 1 A 0 , A 1 A 0 , A 1 A 0 , A 1 A 0 , where A 0 and A 1 are the addressbits applied to the burst logic. The burst logic shown in Fig. 15.9 is also a two-bit logic.15.5.2 Dynamic RAMThe memory cell in the case of a DRAM comprises a capacitor and a MOSFET. The cell holds a valueof ‘1’ when the capacitor is charged and ‘0’ when it is discharged. The main advantage of this typeof memory is its higher density, or more bits per package, compared with SRAM. This is because thememory cell is very simple compared with that of SRAM. Also, the cost per bit is less in the case ofa DRAM. The disadvantage of this type of memory is the leakage of charge stored on the capacitorsof various memory cells when they are storing a ‘1’. To prevent this from happening, each memorycell in a DRAM needs to be periodically read, its charge (or voltage) compared with a reference valueand then the charge restored to the capacitor. This process is known as ‘memory refresh’ and is doneapproximately every 5–10 ms.Figure 15.10 shows the basic memory cell of a DRAM and its principle of operation. The MOSFETacts like a switch. When in the ‘write’ mode (R/W = 0, the input buffers are enabled while theoutput buffers are disabled. When ‘1’ is to be stored in the memory, the ‘data in’ line must be in theHIGH state and the corresponding ‘row line’ should also be in the HIGH state so that the MOSFET isswitched ON. This connects the MOSFET to the ‘data in’ line, and it charges the capacitor to a positivevoltage level. When ‘0’ needs to be stored, the ‘data in’ line is LOW and the capacitor also acquiresthe same level. When the ‘row line’ is taken to the LOW state, the MOSFET is switched OFF and isdisconnected from the bit line. This traps the charge on the capacitor. In ‘read’ mode (R/W = 1, theoutput buffers are enabled while the input buffers are disabled. When the ‘row line’ is taken to HIGHlogic, the MOSFET is switched ON and connects the capacitor to the ‘data out’ line through the outputRowColumnMOSFETCapacitorR/WRefreshRow'Data out'RefreshBufferOutput BufferSense AmpliierColumn'Data in'Input BufferFigure 15.10Basic memory cell of a DRAM.