Digital Electronics: Principles, Devices and Applications

Troubleshooting Digital Circuits and Test Equipment 69516.17.2.5 Storage QualifierThe function of the storage qualifier is to determine which data samples are clocked into the memory.The storage qualifier block looks at the sampled data and tests them against a criterion. If the criterionis met, the clocked sample is stored in the memory. This feature is particularly useful in troubleshootingmicroprocessor architectures. For instance, if the circuit under test is a microprocessor bus, this functioncan be used to separate bus cycles to a specific I/O port from cycles to all other ports or from instructioncycles.16.17.2.6 User InterfaceBenchtop logic analysers typically use a dedicated keyboard and CRT display. Graphical user interfaces(GUIs) similar to those available on personal computers are also available with many products. Also,interfaces such as RS-232, IEEE-488 or local area network (LAN) enable the use of the instrument froma personal computer or a workstation. Remote interfaces are important in manufacturing applications.LAN interfaces have emerged as critical links in research and development activities where theseinstruments can be tied to project databases.16.17.3 Key SpecificationsSome of the important specifications of logic analysers include sample rate, set-up and hold times, probeloading, memory depth and channel count. Trigger resources, the availability of preprocessors/inverseassemblers, nonvolatile storage and the ability of the logic analyser to store time value along withcaptured data are the other key features.16.17.3.1 Sample rateThe sample rate in the timing mode determines the minimum resolvable time interval. Since therelationship of the sample clock and the input signal transition is random, two edges of the same signalcan be measured to an accuracy of two sample periods. Measuring a transition on one signal withrespect to a transition on another signal can also be done with an accuracy of two sample periodsplus whatever skew exists between the channels. In the state mode, the sample rate determines themaximum clock rate that can be measured in the target state machine.16.17.3.2 Set-up and Hold TimesThe set-up and hold time specification in the case of logic analysers is similar to that in the case offlip-flops, registers and memory devices. Like these devices, a logic analyser also needs stable data fora specified time before the clock becomes active. This specified time is the set-up time. The hold timeis the time interval for which the data must be held after the active transition of the clock to enabledata capture. The hold time is typically zero for logic analysers.16.17.3.3 Probe LoadingIt is desired that the target system not be perturbed by probe loading. Logic analysers with a samplingrate of equal to or less than 500 MHz have probe specifications of typically 100K and 6–8 pF. Analysers