Digital Electronics: Principles, Devices and Applications

Logic Families 139V CC = 4.5–5.5 V; propagation delay (for a load resistance of 500 , a load capacitance of 50 pF,V CC = 4.5–5.5 V and an ambient temperature of minimum to maximum) = 11 ns/16 ns (max.) forLOW-to-HIGH and 8 ns/13 ns for HIGH-to-LOW output transitions (74ALS/54ALS); worst-case noisemargin = 0.3 V; fan-out = 20; I CCH (for all four gates) = 0.85 mA; I CCL (for all four gates) = 3 mA;operating temperature range = 0–70 °C (74-series) and −55 to +125 °C (54-series); speed–powerproduct = 4.8 pJ; maximum flip-flop toggle frequency = 70 MHz.5.3.8 Advanced Schottky TTL (74AS/54AS)Figure 5.22 shows the internal schematic of an advanced Schottky TTL NAND gate. The circuit shownis that of one of the four gates inside a quad two-input NAND (type 74AS00 or 54AS00). SalientVCCR110KR22KR750KR626D4Q6R81KQ9Q2D5R32KQ7Input AQ 1AD 2AR 930KQ 8D 6D 7D9D3OutputD 1AQ 3R 41KR 52KD8R11100Q5Input BQ 1BQ4R1025KQ10D2BD1BFigure 5.22NAND gate in the AS-TTL.