Digital Electronics: Principles, Devices and Applications

Troubleshooting Digital Circuits and Test Equipment 663to flip-flops FF-2 and FF-l are examined simultaneously and it is discovered that the clock input toFF-l is delayed from the clock input to FF-2 by more than 15 ns, FF-l will make a transition to thelogic ‘1’ state with the first clock transition. Similarly, if the clock input to FF-0 is delayed by morethan 15 ns from that to FF-l or by more than 30 ns from that to FF-2, even FF-0 is going to makea transition to the logic ‘1’ state with the first relevant transition of the clock signal. And what ismore important is that all other observed outputs for subsequent clock pulses, as shown in Table 16.2,are also valid under these circumstances. The waveforms shown in Fig. 16.6 illustrate how this clockdelay can cause a fault condition. Thus, this seems to be the most probable reason for the present faultcondition.16.3 Troubleshooting Arithmetic CircuitsThe arithmetic circuits also fall into the category of combinational circuits. Therefore, thetroubleshooting tips are similar to those described at length in the previous pages. It would be worthreiterating again that knowledge of the internal structure and functional aspects of the ICs usedhelps a lot in identifying the reasons for a fault. The following troubleshooting exercise illustratesthe point.Example 16.5Figure 16.7 shows a four-bit binary adder–subtractor circuit configured around a four-bit parallelbinary adder (type number 7483) and a quad two-input EX-OR gate (type number 7486). Thearrangement works as an adder when the ADD/SUB input is in the logic ‘0’ state, and as asubtractor when ADD/SUB is in the logic ‘1’ state. The circuit has developed a fault. It is functioningsatisfactorily as a subtractor. However, when it is used as an adder, it is observed that theSUM output is not A + B but A + B + l instead. What do you think is the probable reason forthis behaviour?B3B2B1B0A3 A2 A1 A0ADD/SUB7486A3 A2 A1 A0 B3 B2 B1 B07483 CiC0 S3 S2 S1 S0Figure 16.7 Adder–subtractor circuit (example 16.5).