Digital Electronics: Principles, Devices and Applications

330 Digital ElectronicsInputsGlobalSet/ResetGlobalClockAdditionalProductTerms(from otherMacrocells)Product Term Set1ProductTermAllocator0Product Term ClockSD/T QSRFFRToSwitchMatrixProduct Term ResetProduct Term OEToI/OBlocksFigure 9.26Macrocell architecture.additional product terms from other macrocells in the same logic block, apart from a maximum of fiveproduct terms from within the same macrocell.Figure 9.26 shows the logic diagram of a macrocell typical of macrocells in the logic blocks of mostcontemporary CPLDs. The diagram is self-explanatory. There may be minor variations in devices fromdifferent manufacturers. For example, macrocells in the XC-7000 series CPLDs from Xilinx have twoOR gates fed from a two-bit arithmetic logic unit (ALU) and its output feeds a configurable flip-flop.9.7.2 ApplicationsOwing to their less flexible internal architecture leading to predictable timing performance, high speedand a range of logic capacities, CPLDs find extensive use in a wide assortment of applications. Theseinclude the implementation of random glue logic in prototyping small gate arrays, implementing criticalcontrol designs such as graphics controllers, cache control, UARTs, LAN controllers and many more.CPLDs are fast replacing SPLDs in complex designs. Complex designs using a large number ofSPLDs can be replaced with a CPLD-based design with a much smaller number of devices. Thisis particularly attractive in portable applications such as mobile phones, digital assistants and so on.