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Digital Electronics: Principles, Devices and Applications

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Data Conversion Circuits – D/A <strong>and</strong> A/D Converters 49912.9.11 Code WidthThe code width is the quantum of input voltage change that occurs between the output code transitionsexpressed in LSBs of full scale. Code width uncertainty is the dynamic variation or jitter in the codewidth owing to noise.12.10 A/D Converter TerminologySome of the more commonly used terms while interpreting the specifications <strong>and</strong> salient features ofA/D converters are briefly described in the following paragraphs.12.10.1 Unipolar Mode OperationIn the unipolar mode of operation, the analogue input to the A/D converter varies from 0 to full-scalevoltage of one polarity only.12.10.2 Bipolar Mode OperationAn A/D converter configured to convert both positive <strong>and</strong> negative analogue input voltages is said tobe operating in bipolar mode.12.10.3 CodingCoding defines the nature of the A/D converter output data format. Commonly used formats includestraight binary, offset binary, complementary binary, 2’s complement, low byte <strong>and</strong> high byte.12.10.4 Low Byte <strong>and</strong> High ByteIn A/D converters with a resolution greater than eight bits, some products are offered in high-byte orlow-byte format to simplify their interface with eight-bit microprocessor systems. The low-byte outputcontains the least significant bit <strong>and</strong> some or all of the lower eight bits of the A/D converter output. Inthe high byte, the output contains the MSB <strong>and</strong> some or all of the upper eight bits.12.10.5 Right-Justified Data, Left-Justified DataData bit sets shorter than eight bits are placed in byte-oriented data output format, starting with theright side of the data output transfer register. This could apply to the upper or lower byte. For example,a 12-bit ADC will have four extra bits which could be right justified. Data bit sets shorter than eightbits are placed in left-justified data, starting with the left side of the data output transfer register. Thiscould apply to the lower or upper byte. For example, a 12-bit ADC will have four extra bits whichcould be left justified.

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