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Digital Electronics: Principles, Devices and Applications

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292 <strong>Digital</strong> <strong>Electronics</strong>(a) Since both ENABLE inputs are active, the decoder outputs will therefore be active depending uponthe logic status of the input lines. For the given logic status of the input lines, decoder output line13 will be active <strong>and</strong> therefore LOW. All other output lines will be inactive <strong>and</strong> therefore in thelogic HIGH state.(b) Since neither ENABLE input is active, all decoder outputs will be inactive <strong>and</strong> in the logic HIGHstate.(c) The same as (b).Example 8.10The decoder of example 8.9 is to be used as a 1-of-16 demultiplexer. A logically compatible pulsedwaveform is to be switched between output line 9 <strong>and</strong> line 15 when the logic status of an externalcontrol input is LOW <strong>and</strong> HIGH respectively. Draw the logic diagram indicating the logic status ofENABLE inputs <strong>and</strong> DCBA inputs <strong>and</strong> the point of application of the pulsed waveform.SolutionFigure 8.26 shows the logic diagram. When the external control input is in the logic LOW state, D =HIGH, C = LOW, B = LOW <strong>and</strong> A = HIGH. This means that output line 9 is activated. Whenthe external control input is in the logic HIGH state, D = HIGH, C = HIGH, B = HIGH <strong>and</strong> A =HIGH. This means that output line 15 is activated. In the logic diagram shown in Fig. 8.26, the twoENABLE inputs are tied together <strong>and</strong> the pulsed waveform is applied to a common point. This meansthat either both ENABLE inputs are active (when the input waveform is in the logic LOW state) orinactive (when the input waveform is in the logic HIGH state). Thus, when the input waveform is inthe logic LOW state, output line 9 will be in the logic LOW state <strong>and</strong> all other output lines will be inthe logic HIGH state provided the external control input is also in the logic LOW state. If the externalExternalControl'1’G1G21(A)2(B)4(C)8(D)&741540123456789101112131415Figure 8.26 Example 8.10.

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