Digital Electronics: Principles, Devices and Applications

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374 Digital Electronicsthat, when one of the transistors was in saturation, the other was in cut-off. This implies that, if we hadtaken outputs from the collectors of both transistors, then the two outputs would be complementary.In the flip-flops of various types that are available in IC form, we will see that all these devices offercomplementary outputs usually designated as Q and QThe R-S flip-flop is the most basic of all flip-flops. The letters ‘R’ and ‘S’ here stand for RESETand SET. When the flip-flop is SET, its Q output goes to a ‘1’ state, and when it is RESET it goes toa ‘0’ state. The Q output is the complement of the Q output at all times.10.3.1 R-S Flip-Flop with Active LOW InputsFigure 10.17(a) shows a NAND gate implementation of an R-S flip-flop with active LOW inputs. Thetwo NAND gates are cross-coupled. That is, the output of NAND 1 is fed back to one of the inputsof NAND 2, and the output of NAND 2 is fed back to one of the inputs of NAND 1. The remaininginputs of NAND 1 and NAND 2 are the S and R inputs. The outputs of NAND 1 and NAND 2 arerespectively Q and Q outputs.The fact that this configuration follows the function table of Fig. 10.17(c) can be explained. We willlook at different entries of the function table, one at a time.Let us take the case of R = S = 1 (the first entry in the function table). We will prove that, forR = S = 1, the Q output remains in its existing state. In the truth table, Q n represents the existing stateand Q n+1 represents the state of the flip-flop after it has been triggered by an appropriate pulse at theR or S input. Let us assume that Q = 0 initially. This ‘0’ state fed back to one of the inputs of gate 2ensures that Q = 1. The ‘1’ state of Q fed back to one of the inputs of gate 1 along with S = 1 ensuresthat Q = 0. Thus, R = S = 1 holds the existing stage. Now, if Q was initially in the ‘1’ state and notthe ‘0’ state, this ‘1’ fed back to one of the inputs of gate 2 along with R = 1 forces Q to be in the ‘0’state. The ‘0’ state, when fed back to one of the inputs of gate 1, ensures that Q remains in its existingstate of logic ‘1’. Thus, whatever the state of Q, R = S = 1 holds the existing state.Let us now look at the second entry of the function table where S = 0 and R = 1. We can see thatsuch an input combination forces the Q output to the ‘1’ state. On similar lines, the input combinationS = 1 and R = 0 (third entry of the truth table) forces the Q output to the ‘0’ state. It would beinteresting to analyse what happens when S = R = 0. This implies that both Q and Q outputs shouldgo to the ‘1’ state, as one of the inputs of a NAND gate being a logic ‘0’ should force its output to thelogic ‘1’ state irrespective of the status of the other input. This is an undesired state as Q and Q outputsare to be the complement of each other. The input condition (i.e. R = S = 0) that causes such a situationis therefore considered to be an invalid condition and is forbidden. Figure 10.17(b) shows the logicsymbol of such a flip-flop. The R and S inputs here have been shown as active LOW inputs, which isobvious as this flip-flop of Fig. 10.17(a) is SET (that is, Q = 1) when S = 0 and RESET (that is, Q = 0)when R = 0. Thus, R and S are active when LOW. The term CLEAR input is also used sometimes inplace of RESET. The operation of the R-S flip-flop of Fig. 10.17(a) can be summarized as follows:1. SET = RESET = 1 is the normal resting condition of the flip-flop. It has no effect on the output state ofthe flip-flop. Both Q and Q outputs remain in the logic state they were in prior to this input condition.2. SET = 0 and RESET = 1 sets the flip-flop. Q and Q respectively go to the ‘1’ and ‘0’ state.3. SET = 1 and RESET = 0 resets or clears the flip-flop. Q and Q respectively go to the ‘0’ and ‘1’ state.4. SET = RESET = 0 is forbidden as such a condition tries to set (that is, Q = 1 ) and reset (thatis, Q = 1) the flip-flop at the same time. To be more precise, SET and RESET inputs in the R-Sflip-flop cannot be active at the same time.The R-S flip-flop of Fig. 10.17(a) is also referred to as an R-S latch. This is because any combinationat the inputs immediately manifests itself at the output as per the truth table.
Flip-Flops and Related Devices 375S1QR2Q —(a)SQRSFFRQ —(b)OperationModeNo changeSETRESETForbiddenS1010R1100Qn+1Qn10—(c)Figure 10.17R-S flip-flop with active LOW inputs.10.3.2 R-S Flip-Flop with Active HIGH InputsFigure 10.18(a) shows another NAND gate implementation of the R-S flip-flop. Figures 10.18(b) and(c) respectively show its circuit symbol and function table. Such a circuit would have active HIGHinputs. The input combination R = S = 1 would be forbidden as SET and RESET inputs in an R-Sflip-flop cannot be active at the same time.
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Digital ElectronicsDigital Electron
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Copyright © 2007John Wiley & Sons
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ContentsPrefacexxi1 Number Systems
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ContentsixReview Questions 67Proble
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Contentsxi6.3.8 Theorem 8 1966.3.9
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Contentsxiii9.11.3 Verilog 3399.11.
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Contentsxv12.2.5 Nonlinearity and D
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Contentsxvii13.10.3 80286 Microproc
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ContentsxixReview Questions 650Prob
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PrefaceDigital electronics is essen
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Prefacexxiiilogic analysers, freque
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Number Systems 3The value or magnit
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Number Systems 5The 1’s complemen
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Number Systems 7• The fractional
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Number Systems 9• The octal equiv
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Number Systems 11Solution• The gi
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Number Systems 13Hexadecimal system
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Number Systems 15Byte-1 Byte-2 Byte
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Number Systems 17Therefore, the exp
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2Binary CodesThe present chapter is
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Binary Codes 212.1.3 Higher-Density
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Binary Codes 23Fractional part = .7
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Binary Codes 252.3.2 Gray Code-Bina
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Binary Codes 27Solution(a) The bina
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Binary Codes 29Table 2.6(continued)
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Binary Codes 39fabDPegdc(a)afbegcDP
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Binary Codes 412.6.1 Parity CodeA p
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Binary Codes 43Table 2.9Generation
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Binary Codes 456. What is a parity
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48 Digital ElectronicsTable 3.1Bina
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50 Digital ElectronicsCase 1• Con
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52 Digital Electronics2. (AF1.B3) 1
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54 Digital ElectronicsCase 2• Let
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56 Digital ElectronicsExample 3.4Su
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58 Digital Electronics0110 1000 rep
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60 Digital ElectronicsTable 3.3Mult
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62 Digital ElectronicsTable 3.6algo
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64 Digital ElectronicsTable 3.8 Exa
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66 Digital Electronicsquotient is g
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68 Digital Electronics5. Prove that
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70 Digital ElectronicsIf the two vo
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72 Digital ElectronicsABCY=A+B+C(a)
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74 Digital ElectronicsABY=A.B(a)A00
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76 Digital ElectronicsXY=X(a)XY=XX0
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78 Digital ElectronicsAY1BCY(a)ABCD
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80 Digital ElectronicsABYABY=A+B(a)
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82 Digital ElectronicsABCDY=A.B.C.D
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84 Digital Electronics'1''1'ab c d
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86 Digital ElectronicsAY=A(a)ABY=A+
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88 Digital ElectronicsAYBEA00001111
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90 Digital ElectronicsABCD(AB+CD+EF
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92 Digital Electronics(a)(b)4V (vol
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94 Digital Electronics'1'I/PI/P(Vol
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96 Digital ElectronicsIOHIIHIIHIIH(
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98 Digital ElectronicsThe output of
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100 Digital ElectronicsE1LLHE2LHXOp
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102 Digital Electronics1A1B2A2B3A3B
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104 Digital Electronics4.13.2 AND G
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106 Digital ElectronicsFigure 4.53(
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108 Digital ElectronicsTable 4.1(co
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110 Digital Electronics(c) a three-
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114 Digital Electronics6. It is pro
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116 Digital Electronicsother and th
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118 Digital Electronics5.1.2.3 ECL
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120 Digital Electronics• LOW-leve
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122 Digital Electronics• Enable t
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124 Digital ElectronicsExample 5.2R
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126 Digital Electronics+VCC+VCCR 3I
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128 Digital Electronics4K 1301.6KVC
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130 Digital Electronicsbe in cut-of
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132 Digital ElectronicsVCC4K1.6KInp
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134 Digital Electronicslow-power TT
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136 Digital Electronics5.3.5.1 Char
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138 Digital ElectronicsVCCR 137KR 2
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140 Digital Electronicsfeatures of
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142 Digital ElectronicsFigure 5.24H
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144 Digital Electronics+VCC+VCCR1IO
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146 Digital ElectronicsFigure 5.30
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148 Digital Electronics5.4.1.2 MECL
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150 Digital ElectronicsFigure 5.33E
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152 Digital Electronicsfunctions as
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154 Digital ElectronicsVDDAQ1BQ 2Y=
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156 Digital ElectronicsVDDAQ 1BQ2Q5
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158 Digital ElectronicsFigure 5.42T
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160 Digital Electronics+VDDQ7Q8Q5Q6
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162 Digital ElectronicsFigure 5.46C
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166 Digital Electronicslogic status
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168 Digital Electronics5.5.2.4 74AC
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170 Digital Electronics+VDDA+VDDA -
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172 Digital Electronics+VDDAQ 1Q 3Q
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174 Digital Electronicsthe conducti
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176 Digital Electronics+VRQ3Q4AAQ 2
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178 Digital Electronics74S00174S002
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180 Digital Electronicsvoltage of 5
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182 Digital Electronics+5V10KI/PTTL
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184 Digital ElectronicsI/PCMOSCMOS-
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6Boolean Algebra andSimplification
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Boolean Algebra and Simplification
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234 Digital Electronics'n'InputsCom
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236 Digital Electronicsof Boolean e
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238 Digital ElectronicsC in C out11
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240 Digital ElectronicsABC inABC in
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242 Digital ElectronicsABHalfSubtra
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244 Digital ElectronicsB inABDB o(a
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246 Digital ElectronicsFigure 7.19F
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248 Digital ElectronicsTable 7.1 Re
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250 Digital ElectronicsExample 7.1F
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252 Digital ElectronicsSolutionLet
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254 Digital ElectronicsB 7 B 6 B 5
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256 Digital Electronicsotherwise ha
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260 Digital Electronics7.7 Arithmet
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264 Digital ElectronicsTable 7.2 Fu
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266 Digital ElectronicsTable 7.3Com
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268 Digital ElectronicsFurther Read
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270 Digital ElectronicsI 0I 1I 2I 3
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272 Digital ElectronicsI 0I 12-to-1
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274 Digital ElectronicsI 0I 1YI 2I
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276 Digital ElectronicsTable 8.2 Im
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278 Digital ElectronicsSolution•
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280 Digital Electronics8.1.4 Cascad
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282 Digital ElectronicsD 0 D 1 D 2
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284 Digital ElectronicsExample 8.4W
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286 Digital ElectronicsAB2-to-40123
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288 Digital ElectronicsABC2 2012345
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290 Digital Electronics0CBA12 22F3-
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292 Digital Electronics(a) Since bo
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294 Digital ElectronicsTable 8.12(c
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296 Digital ElectronicsD 0I 0I 1S 0
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298 Digital ElectronicsFurther Read
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300 Digital Electronicslogic functi
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302 Digital Electronics3. In the ca
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304 Digital ElectronicsD C B AProgr
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306 Digital Electronicsa GAL device
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308 Digital Electronicslarge memory
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310 Digital ElectronicsA B C D EHar
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312 Digital ElectronicsSolution(a)
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314 Digital ElectronicsInputs(n)(k)
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316 Digital ElectronicsABCiSCoFigur
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318 Digital ElectronicsAA 1 0B1B000
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320 Digital ElectronicsA1A0B1B0O/P-
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Counters and Registers 425Table 11.
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Counters and Registers 427Presettab
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Counters and Registers 429Clk(D)Q 0
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Counters and Registers 431Input AAO
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Counters and Registers 433ClockA-Ou
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Counters and Registers 435PLP3 P2 P
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Counters and Registers 437+V CCGNDU
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Counters and Registers 441The circu
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Counters and Registers 445CX (C) 1B
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Counters and Registers 447Figure 11
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Counters and Registers 449to the dr
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Figure 11.43 Logic diagram of IC 74
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Counters and Registers 45911.13 Shi
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Counters and Registers 461Clock-Inp
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Counters and Registers 4631JFClockC
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Counters and Registers 465R0(1)R0(2
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Counters and Registers 467(9)CLK C1
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Counters and Registers 4711OutputCJ
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12Data Conversion Circuits - D/Aand
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Data Conversion Circuits - D/A and
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{Data Conversion Circuits - D/A and
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(Data Conversion Circuits - D/A and
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526 Digital ElectronicsAddress BusM
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528 Digital Electronicsyear 1973. I
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530 Digital Electronicsto the addre
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532 Digital ElectronicsDemultiplexe
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534 Digital Electronicscounter and
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536 Digital ElectronicsOperationReg
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538 Digital Electronics13.6.1.2 Pow
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540 Digital Electronics13.7 Program
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542 Digital ElectronicsX1X2RESET OU
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544 Digital ElectronicsTable 13.3Si
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{{546 Digital ElectronicsSystem Dat
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{548 Digital ElectronicsBus Interfa
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550 Digital ElectronicsData Registe
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552 Digital ElectronicsBarrelShifte
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554 Digital ElectronicsSequencer an
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556 Digital Electronics64-bit inter
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558 Digital Electronicsfrom the Pen
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560 Digital ElectronicsPentium bran
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562 Digital Electronicsfor microcom
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564 Digital Electronics4. Briefly d
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566 Digital ElectronicsROMEEPROMRAM
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568 Digital ElectronicsFromSensorsT
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570 Digital ElectronicsThe digital-
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572 Digital Electronicsare embedded
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574 Digital Electronicscomprises on
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576 Digital Electronics14.3.2 Mappi
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578 Digital ElectronicsRegister-1Re
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580 Digital ElectronicsYet another
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582 Digital ElectronicsT2/P1.0T2EX/
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584 Digital Electronics14.5.1.8 68H
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586 Digital ElectronicsPA7/PAI/OC1P
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588 Digital ElectronicsPeripheral-r
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*590 Digital ElectronicsPP3/PW3PP4P
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592 Digital Electronicssignal-proce
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594 Digital ElectronicsV CCMicrocon
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596 Digital ElectronicsV CCI/O PinI
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598 Digital Electronicsdp1234567abc
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600 Digital ElectronicsV CC3V CC2Mi
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602 Digital ElectronicsReview Quest
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15Computer FundamentalsThis chapter
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Computer Fundamentals 607Secondary
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Computer Fundamentals 60915.3.3 Cla
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Computer Fundamentals 611CPURegiste
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Computer Fundamentals 613SelectData
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Computer Fundamentals 615DataInputI
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Computer Fundamentals 6171t RCAddre
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Computer Fundamentals 619as in the
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Computer Fundamentals 6211MUX1RAS1C
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Computer Fundamentals 623CLKCentral
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Computer Fundamentals 6251AddressIn
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Computer Fundamentals 627Row-0+V CC
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Computer Fundamentals 629erasabilit
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Computer Fundamentals 631code conve
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Computer Fundamentals 633AB 3Addres
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Computer Fundamentals 635and RAM-2
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Computer Fundamentals 637A 0 A 1 A
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Computer Fundamentals 63912 34 5678
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Computer Fundamentals 64115.8.2.1 I
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Computer Fundamentals 64315.9.1 Inp
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Computer Fundamentals 645The plasma
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Computer Fundamentals 647the disk s
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Computer Fundamentals 649The read o
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Computer Fundamentals 6512. A certa
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654 Digital ElectronicsFault detect
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656 Digital Electronics16.1.2.1 Ope
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658 Digital ElectronicsI 1456I 2121
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660 Digital ElectronicsClk-11Clk1D1
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662 Digital Electronicsthe clock si
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664 Digital ElectronicsSolution•
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666 Digital Electronics16.6.1 Advan
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670 Digital ElectronicsTriggerFigur
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672 Digital ElectronicsSignalSADC M
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674 Digital Electronics16.12.1.2 Ve
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678 Digital ElectronicsProbe BodyOs
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680 Digital ElectronicsTime BaseOsc
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682 Digital ElectronicsThe resoluti
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684 Digital ElectronicsI/PSamplerLP
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686 Digital ElectronicsReferenceOsc
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688 Digital ElectronicsFrequencyCon
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690 Digital Electronicssynthesizer
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692 Digital Electronicsto indicate
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694 Digital Electronics16.17.2.4 Cl
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696 Digital Electronicshaving a sam
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698 Digital Electronicsthe monitor
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700 Digital Electronicsetc., are th
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704 Digital Electronics(c) accuracy
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Index1’s complement 5, 610’s co
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Index 709A/D converter terminology
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Index 711Binary-to-hex conversion 1
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Index 713CoolRunner 347-8Counter ty
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Index 715Encoder 280-3EPROM 612, 62
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Index 717Hybrid computer 608Hystere
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Index 719Logic gates (Continued)NAN
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Index 721Multivibrator 357-71astabl
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Index 723Power supply decoupling 14
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Index 725Serial-in serial-out shift
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Index 727UP/DOWN counters 425-6US A
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