Digital Electronics: Principles, Devices and Applications

414 Digital Electronics1ClockJFF0Q0JFF1Q1JFF2Q2JFF3Q3KKKKQ0 Q1 Q2 Q3(a)1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16Clock-InputQ0-OutputQ1-OutputQ 2 -OutputQ3-Output(b)Figure 11.2Four-bit binary ripple counter.to ‘1’. The Q 2 and Q 3 outputs remain unaffected. Therefore, immediately after the occurrence of thesecond HIGH-to-LOW transition of the clock signal, Q 0 = 0, Q 1 = 1, Q 2 = 0 and Q 3 = 0. On similarlines, we can explain the logic status of Q 0 , Q 1 , Q 2 and Q 3 outputs immediately after subsequent clocktransitions. The logic status of outputs for the first 16 relevant (HIGH-to-LOW in the present case)clock signal transitions is summarized in Table 11.1.Thus, we see that the counter goes through 16 distinct states from 0000 to 1111 and then, on theoccurrence of the desired transition of the sixteenth clock pulse, it resets to the original state of 0000from where it had started. In general, if we had N flip-flops, we could count up to 2 N pulses before thecounter resets to the initial state. We can also see from the Q 0 , Q 1 , Q 2 and Q 3 waveforms, as shown