Digital Electronics: Principles, Devices and Applications

Computer Fundamentals 6251AddressInputOldAddressNewAddress100CS1001DataOutputHi-ZStateDataOutputValid0t OEt ACCtFigure 15.15Typical timing diagram of a ROM READ operation.of information. As preparation of a mask is an expensive proposition, mask-programmed ROM iseconomical only when manufactured in large quantities. The limitation of such a ROM is that, onceprogrammed, it cannot be reprogrammed.The basic storage element is an NPN bipolar transistor, connected in common-collector configuration,or a MOSFET in common drain configuration. Figures 15.16(a) and (b) show a MOSFET-based basiccell connection when storing a ‘1’ and ‘0’ respectively. As is clear from the figure, the connection ofthe ‘row line’ to the gate of the MOSFET stores ‘1’ at the location when the ‘row line’ is set to level‘1’. A floating-gate connection is used to store ‘0’. Figures 15.16(c) and (d) show the basic bipolarmemory cell connection when storing a ‘1’ and ‘0’ respectively.Figure 15.17 shows the internal structure of a 4 × 4 bipolar mask-programmed ROM. The dataprogrammed into the ROM are given in the adjoining truth table. The transistors with an open basestore a ‘0’, whereas those with their bases connected to the corresponding decoder output store a ‘1’.As an illustration, transistors Q 30 , Q 20 , Q 10 and Q 00 in row 0 store ‘1’, ‘0’, ‘1’ and ‘0’ respectively.The stored information in a given row is available at the output when the corresponding decoder isenabled, and that ‘row line’ is set to level ‘1’. The output of the memory cells appears at the columnlines. For example, when the address input is ‘11’, row 3 is enabled and the data item at the output is0110.