Digital Electronics: Principles, Devices and Applications

Troubleshooting Digital Circuits and Test Equipment 687VCOModulusControl− . Nor(N+1)f ref × (NxF)f refPhaseDetectorAnalogAdderLoopFilterD/AConverterAccumulatorBCD RegisterBCDAdderMSBCarry Out'F' InputFigure 16.28Fractional N synthesis.two inputs to the phase detector tends to become 360 , which is the maximum the phase detector cantolerate without going out of range, the phase of the divider output (which is ahead of the referenceinput in phase) is retarded by 360 by either changing the divider modulus to N +1 momentarily or byany other means. In the architecture shown, the modulus is changed to accomplish this on receiving acommand from the BCD adder at the time of accumulator overflow.16.15.3 Sampled Sine Synthesis (Direct Digital Synthesis)This method of frequency synthesis is based on generating the waveform of desired frequency byfirst producing the samples as they would look if the desired waveform were sampled or digitizedaccording to the Nyquist sampling theorem, and then interpolating among these samples to constructthe waveform. As the frequency is the rate of change in phase, this information is made use of togenerate samples. The sine of different phase values is stored in a memory, which is addressed by phaseincrement information stored in an accumulator. Figure 16.29 shows a simplified block schematicrepresentation of direct digital synthesis. When the accumulator is clocked at a fixed frequency, thecontents of the accumulator jump by the phase increment whose digital equivalent information is storedin the phase increment register (PIR). By changing the contents of the PIR, the output frequency canbe changed. The rate at which the look-up table in the memory is addressed is given by the clockfrequency and phase increment during one clock period as given by the PIR contents. For instance, ifthe contents of the PIR represented a phase angle of 36 , then the digital samples present at the output