Digital Electronics: Principles, Devices and Applications

662 Digital Electronicsthe clock signal. The clock signals appearing at the input terminals of the three flip-flops, when seenindividually, are observed to be clean and free of any noise content.SolutionInitially, Q 2 = Q l = Q 0 = 0 and D 2 = l as D 2 is fed from Q 0 . Therefore, with the occurrence of thefirst clock pulse, Q 2 is expected to go to the logic ‘1’ state. Since D l = D 0 = 0, Q l and Q 0 are expectedto remain in the logic ‘0’ state. However, Q 2 , Q l and Q 0 are observed to make a transition to the logic‘1’ state. Now this could have been possible if D 2 = D 1 = D 0 = 1, which is not the case. This wouldbe remotely possible if there were an external or an internal open at all the D inputs, making themfloating inputs. Since the ICs used here are TTL ICs, these floating inputs would be treated as logicHIGH. All this seems to be valid for only the first clock pulse, because, if this were true, the threeoutputs would subsequently stay in the logic ‘1’ state. Here, all outputs are observed to be toggling.Whether there is any internal or external open or short can be verified with a continuity check using amultimeter.There is another possibility. As we know, clock skew is a problem that quite often bothers flipfloptiming. Whether or not the fault could possibly be due to the clock skew problem will now beexamined. This is not an arbitrary choice. If the statement of the problem is carefully read, it is statedthere that the given circuit is only a part of a bigger circuit, and also that clock signals have beenobserved only individually at the relevant inputs of different flip-flops. It is therefore quite possiblethat the clock signals at the clock inputs of different flip-flops are not synchronous. If the clock inputsClk-2Clk-1Clk-0Q215nsQ115nsQ015nsFigure 16.6 Waveforms (troubleshooting exercise 16.4).