Digital Electronics: Principles, Devices and Applications

Multiplexers and Demultiplexers 281S 3D 0D 1D 2D 3D 4D 5D 6I 0I 1I 7E8-to-1MUXYD 7S 0S 2S 1S 0S 1D 8D 9D 10D 11D 12D 13D 14D 15S 0I 0I 1I 7ES 28-to-1FMUXYS 2S 1Figure 8.14 Example 8.3.The eight input lines would have 2 8 = 256 possible combinations. However, in the case of anoctal-to-binary encoder, only eight of these 256 combinations would have any meaning. The remainingcombinations of input variables are ‘don’t care’ input combinations. Also, only one of the input linesat a time is in logic ‘1’ state. Figure 8.15 shows the hardware implementation of the octal-to-binaryencoder described by the truth table in Table 8.8. This circuit has the shortcoming that it produces anall 0s output sequence when all input lines are in logic ‘0’ state. This can be overcome by having anadditional line to indicate an all 0s input sequence.8.2.1 Priority EncoderA priority encoder is a practical form of an encoder. The encoders available in IC form are allpriority encoders. In this type of encoder, a priority is assigned to each input so that, when morethan one input is simultaneously active, the input with the highest priority is encoded. We willillustrate the concept of priority encoding with the help of an example. Let us assume that the octalto-binaryencoder described in the previous paragraph has an input priority for higher-order digits.Let us also assume that input lines D 2 , D 4 and D 7 are all simultaneously in logic ‘1’ state. Inthat case, only D 7 will be encoded and the output will be 111. The truth table of such a priority