Digital Electronics: Principles, Devices and Applications

132 Digital ElectronicsVCC4K1.6KInput AInput BD1Q1D2Q21KQ 3OutputYGNDFigure 5.14NAND gate with an open collector output.+VCC+VCC130Q 31130Q 32Q 41Q42Gate–1Gate–2Figure 5.15Totem-pole output gates tied at the output.gates have been tied together. Let us assume that the output of one of the gates, say gate-2, is LOW,and the output of the other is HIGH. The result is that a relatively heavier current flows through Q 31and Q 42 . This current, which is of the order of 50–60 mA, exceeds the I OL (max.) rating of Q 42 . Thismay eventually lead to both transistors getting damaged. Even if they survive, V OL (max.) of Q 42 isno longer guaranteed. In view of this, although totem-pole output TTL gates are not tied together, anaccidental shorting of outputs is not ruled out. In such a case, both devices are likely to get damaged.In the case of open collector devices, deliberate or nondeliberate, shorting of outputs produces ANDingof outputs with no risk of either damage or compromised performance specifications.5.3.2.8 Tristate GateTristate gates were discussed in Chapter 4. A tristate gate has three output states, namely the logicLOW state, the logic HIGH state and the high-impedance state. An external enable input decides