Digital Electronics: Principles, Devices and Applications

404 Digital Electronics+V+V21+V0SwitchMovedfrom Pos-1to Pos-2SwitchMovedfrom Pos-2to Pos-1Figure 10.48Switch debounce circuit.always leads to a ‘1’ level at the output, and breaking of contact also leads to a ‘1’ level at the outputowing to the fact that the contact break produces a ‘1’ level at both inputs of the latch which forcesthe output to hold its existing logic state. The fact that when the switch is brought back to position 1the output makes a neat transition to a ‘0’ level can be explained on similar lines.10.10.2 Flip-Flop SynchronizationConsider a situation where a certain clock input, which works in conjunction with various synchronousinputs, is to be gated with an asynchronously generated gating pulse, as shown in Fig. 10.49. Theoutput in this case has the clock pulses at one or both ends shortened in width, as shown in Fig. 10.49.This problem can be overcome and the gating operation synchronized with the help of a flip-flop, asshown in Fig. 10.50.10.10.3 Detecting the Sequence of EdgesFlip-flops can also be used to detect the sequence of occurrence of rising and falling edges. Figure10.51 shows how a flip-flop can be used to detect whether a positive-going edge A follows or precedesanother positive-going edge B. The two edges are respectively applied to D and clock inputs of aFigure 10.49Gating of a clock signal.