Digital Electronics: Principles, Devices and Applications

620 Digital Electronicsbuffer. The refresh operation is performed by setting R/W = 1 and by enabling the refresh buffer.There are two basic modes of refreshing the memory, namely the burst refresh and distributed refreshmodes. In burst refresh mode, all rows in the memory array are refreshed consecutively during therefresh burst cycle. In distributed refresh mode, each row is refreshed at intervals interspaced between‘read’ and ‘write’ operations.15.5.2.1 DRAM ArchitectureThe architecture of DRAM memory is somewhat different from that of SRAM memory. Row andcolumn address lines are usually multiplexed in a DRAM. This is done to reduce the number ofpins on the package. Row address select (RAS) and column address select (CAS) inputs are used toindicate whether a row or a column is to be addressed. Address multiplexing is particularly attractivefor higher-capacity DRAMs. A 4 MB RAM, for instance, would require 22 address inputs (2 22 = 4M)Figure 15.11 shows the architecture of a 16K × 1 DRAM. The heart of a DRAM is an array of singlebitmemory cells. Each cell has a unique position as regards row and column. Other important blocksinclude address decoders (row decoder and column decoder) and refresh control and address latches(row address latch and column address latch). As can be seen from the figure, seven address lines aretime multiplexed at the beginning of the memory cycle by the RAS and CAS lines. Firstly, the seven-bitaddress (A 0 –A 6 is latched into the row address latch, and then the seven-bit address is latched intothe column address latch (A 7 –A 13 . They are then decoded to select the particular memory location.Larger word sizes can be achieved by combining more than one chip. This is discussed in the nextsection. Figures 15.12(a) and (b) respectively show the timing diagrams for read and write operations.A DRAM is relatively slower than a SRAM. The typical access time is in the range 100–250 ns.RefreshCircuitryRefreshControl andTiming SignalsMultiplexedAddress BusA0RowAddresslatchA6DataSelectorRowDecoder12Memory array128 rows× 128 Column1271281 2 127 128A7ColumnAddresslatchA13ColumnDecoder12127128I/O BufferandSenseamplifiersData outData inCASRASR/WCSFigure 15.11Architecture of a 16K × 1 DRAM.