Digital Electronics: Principles, Devices and Applications

Flip-Flops and Related Devices 379time being, let us first see how the flip-flop of the previous section can be transformed into a clockedflip-flop. Figure 10.21(a) shows the logic implementation of a clocked flip-flop that has active HIGHinputs. The function table for the same is shown in Fig. 10.21(b) and is self-explanatory.The basic flip-flop is the same as that shown in Fig. 10.17(a). The two NAND gates at the inputhave been used to couple the R and S inputs to the flip-flop inputs under the control of the clocksignal. When the clock signal is HIGH, the two NAND gates are enabled and the S and R inputs arepassed on to flip-flop inputs with their status complemented. The outputs can now change states as perthe status of R and S at the flip-flop inputs. For instance, when S = 1 and R = 0 it will be passed on as0 and 1 respectively when the clock is HIGH. When the clock is LOW, the two NAND gates producea ‘1’ at their outputs, irrespective of the S and R status. This produces a logic ‘1’ at both inputs of theflip-flop, with the result that there is no effect on the output states. Figure 10.22(a) shows the clockedR-S flip-flop with active LOW R and S inputs. The logic implementation here is a modification ofthe basic R-S flip-flop in Fig. 10.18(a). The truth table of this flip-flop, as given in Fig. 10.22(b), isself-explanatory.S1QClkR 2Q(a)SRClkQn+1000Qn001Qn010Qn0110100Qn1011110Qn111Invalid(b)Figure 10.21Clocked R-S flip-flop with active HIGH inputs.