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Digital Electronics: Principles, Devices and Applications

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Microcontrollers 58314.5.1.3 80C31RA + /8XC51RA + /RB + /RC + (Dallas Semiconductor <strong>and</strong> Othermanufacturers)The same as 80C51 except for the size of ROM <strong>and</strong> RAM, which is 0K/8K/16K/32K (ROM) <strong>and</strong> 512bytes (RAM).14.5.1.4 8XC51RD + (Dallas Semiconductor <strong>and</strong> Other Manufacturers)The same as 80C51 except for the size of ROM <strong>and</strong> RAM, which is 64K (ROM) <strong>and</strong> 1024 bytes(RAM).14.5.1.5 80C32/8XC52/54/58 (Dallas Semiconductor <strong>and</strong> Other Manufacturers)The same as 80C51 except for the size of ROM <strong>and</strong> RAM, which is 0K/8K/16K/32K (ROM) <strong>and</strong> 256bytes (RAM).14.5.1.6 89C51 (ATMEL <strong>and</strong> Other Manufacturers)Microcontroller-related FeaturesMCS-51 architecture, CMOS technology, 4K × 8 of in-system reprogrammable ROM, 128 × 8 internalRAM, memory addressing capability of 64K (ROM <strong>and</strong> RAM), special-function registers, six interruptsources, two power-saving modes (IDLE <strong>and</strong> POWER DOWN modes), a clock speed range of 0–24MHz, low EMI (inhibit ALE), three package style options (40-pin dual in-line, 44-pin plastic leadedchip carrier <strong>and</strong> 44-pin plastic quad flat pack) <strong>and</strong> compatible with the industry-st<strong>and</strong>ard MCS-51instruction set <strong>and</strong> pin-out.Peripheral-related FeaturesTwo 16-bit counters/timers, 32 programmable I/O lines <strong>and</strong> a programmable serial channel.Architecture <strong>and</strong> Pin Connection DiagramThe architecture <strong>and</strong> pin connection diagram are the same as those given earlier for the case of the80C51 family of microcontrollers in Fig. 14.16 (architecture) <strong>and</strong> Fig. 14.17 (pin connection diagram).14.5.1.7 68HC05 Family of Microcontrollers (Freescale Semiconductor)Microcontroller-related FeaturesFully static chip design using a st<strong>and</strong>ard eight-bit M68HC05 core, a clock speed of 4 MHz, 920bytes of on-chip RAM, 32K of ROM, 7932 bytes of EEPROM (maximum values across the family ofdevices), power-saving WAIT mode <strong>and</strong> available in 40-pin DIP <strong>and</strong> 42-pin SDIP package styles.Peripheral-related FeaturesTwo serial interface channels, a multifunction timer with periodic interrupt, eight A/D converterchannels, three PWM channels <strong>and</strong> 80 I/O lines (maximum values across the family of devices).

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