Digital Electronics: Principles, Devices and Applications

Computer Fundamentals 623CLKCentralProcessingUnit(CPU)CacheControllerMainMemoryHardDiskL1 CacheL2 CacheAddressBusDataBusFigure 15.13Cache memory in a computer system.15.6.1 ROM ArchitectureThe internal structure or architecture of a ROM comprises three basic parts, namely the array ofmemory cells, the address decoder and the output buffers. The address decoder comprises a singledecoder in the case of small memories. In the case of large memories it comprises two decodersreferred to as row and column decoders. The operation of a ROM can be best explained with the helpof the simplified representation of a 32 × 8 ROM, as shown in Fig. 15.14.The array of memory cells stores the data to be programmed into the ROM. The number of memorycells in a row equals the word size, and the number of memory cells in a column equals the number ofsuch words to be stored. In the memory shown in Fig. 15.14, the word size is eight bits and the numberof words is 32. The data outputs of each of the memory cells in the array are connected to an internaldata bus that runs through the entire circuit. The address decoder, a 1-of-32 decoder in this case,sets the corresponding ‘row line’ HIGH when a binary address is applied at its input lines. A five-bitaddress code (A 4 A 3 A 2 A 1 A 0 is needed to address 32 memory cells. As an illustration, an address codeof 10011 will identify the nineteenth rowThe output is read from the column lines. The data placed onthe internal data bus by the memory cells are fed to the output buffers. CS is an active LOW input usedto select the memory device. In the case of larger memories, the address decoder comprises row as wellas column decoders. Let us consider a 2K-bit ROM device with 256 × 8 organization. The memory isarranged in the format of a 32 × 64 matrix instead of a 256 × 8 matrix. Five of the address lines areconnected to the row decoder, and the remaining three lines are connected to the column decoder. Therow decoder is a 1-of-32 decoder, and it selects one of the 32 rows. The column decoder compriseseight 1-of-8 decoders. It selects eight of the total 64 columns. Thus, an eight-bit word appears on thedata output when the address is applied and CS = 0.Figure 15.15 shows the typical timing diagram of a ROM read operation. It shows that there is atime delay that occurs between the application of an address input and the availability of correspondingdata at the output. It is this time delay that determines the ROM operating speed. This time delay is