Digital Electronics: Principles, Devices and Applications

156 Digital ElectronicsVDDAQ 1BQ2Q5Y=(A+B)Q3 Q 4Q 6Figure 5.40Two-input OR in CMOS.Figure 5.41(b) shows the internal schematic of a two-input EX-OR gate. MOSFETs Q 1 –Q 4constitute the NOR gate. MOSFETS Q 5 and Q 6 simulate ANDing of A and B, and MOSFETQ 7 provides ORing of the NOR output with ANDed output. Since MOSFETs Q 8 –Q 10 make upthe complement of the arrangement of MOSFETs Q 5 –Q 7 , the final output is inverted. Thus, theschematic of Fig. 5.41(b) implements the logic arrangement of Fig. 5.41(a) and hence a two-inputEX-OR gate.5.5.1.7 EXCLUSIVE-NOR GateAn EXCLUSIVE-NOR gate is implemented using the logic diagram of Fig. 5.42(a). As is evidentfrom the figure, the output of this logic arrangement can be expressed byABA + B = A + BA + B = EX − NOR function (5.2)Figure 5.42(b) shows the internal schematic of a two-input EX-NOR gate. MOSFETs Q 1 –Q 4constitute the NAND gate. MOSFETS Q 5 and Q 6 simulate ORing of A and B, and MOSFETQ 7 provides ANDing of the NAND output with ORed output. Since MOSFETs Q 8 –Q 10 make upthe complement of the arrangement of MOSFETs Q 5 –Q 7 , the final output is inverted. Thus, theschematic of Fig. 5.42(b) implements the logic arrangement of Fig. 5.42(a) and hence a two-inputEX-NOR gate.