Digital Electronics: Principles, Devices and Applications

Data Conversion Circuits – D/A and A/D Converters 509conversion speed at the cost of added complexity. Increase in conversion speed is accomplishedby carrying out integration from reference voltage at two distinct rates, a high-speed rate and alow-speed rate. The counter is also divided into two sections, one for MSB bits and the other forLSB bits. A properly designed triple-slope converter achieves increased conversion speed withoutcompromising the inherent linearity, differential linearity and stability characteristics of the dual-slopeconverter.Bias currents, offset voltages and gain errors associated with operational amplifiers used as integratorsand comparators do introduce some errors. These can be cancelled by using additional charge/dischargecycles and then using the results to correct the initial measurement. One such A/D converter is thequad-slope converter which uses two charge/discharge cycles as compared with one charge/dischargecycle in the case of the dual-slope converter. Quad-slope A/D converters have a much higher accuracythan their dual-slope counterparts.12.11.7 Sigma-Delta A/D ConverterThe sigma-delta A/D converter employs a different concept from what has been discussed so far for thecase of various types of A/D converter. While the A/D converters covered so far rely on sampling ofthe analogue signal at the Nyquist frequency and encode the absolute value of the sample, in the case ofa sigma-delta converter, as explained in the following paragraphs, the analogue signal is oversampledby a large factor (i.e. the sampling frequency is much larger than the Nyquist value), and also it isnot the absolute value of the sample but the difference between the analogue values of two successivesamples that is encoded by the converter.In the case of the A/D converters discussed prior to this and sampled at the Nyquist rate f s , theRMS value of the quantization noise is uniformly distributed over the Nyquist band of DC to f s /2, asshown in Fig. 12.38(a). The signal-to-noise ratio for a full-scale sine wave input in this case is given byS/N = (6.02n + 1.76) dB, n being the number of bits. The only way to increase the signal-to-noise ratiois by increasing the number of bits. On the other hand, a sigma-delta converter attempts to enhance thesignal-to-noise ratio by oversampling the analogue signal, which has the effect of spreading the noisespectrum over a much larger bandwidth and then filtering out the desired band. If the analogue signalwere sampled at a rate of Kf s , the quantization noise would be spread over DC to Kf s /2, as shown inFig. 12.38(b). K is a constant referred to as the oversampling ratio. The enhanced S/N ratio meanshigher resolution, which is achieved by other types of A/D converter by way of increasing the numberof bits.It may be mentioned here that, if we simply use oversampling to improve the resolution, it would berequired to oversample by a factor of 2 2N to achieve an N -bit increase in resolution. The sigma-deltaconverter does not require to be oversampled by such a large factor because it not only limits thesignal pass band but also shapes the quantization noise in such a way that most of it falls outside thispass band, as shown in Fig. 12.38(c). The following paragraphs explain the operational principle ofthe sigma-delta A/D converter.The heart of the sigma-delta converter is the delta modulator. Figure 12.39 shows a block schematicrepresentation of a delta modulator, which is basically a one-bit quantizer of the flash type (singlecomparator). The output of the delta modulator is a bit stream of 1s and 0s, with the number of 1srelative to the number of 0s over a given number of clock cycles indicating the amplitude of theanalogue signal over that time interval. An all 1s sequence over a given interval corresponds to themaximum positive amplitude, and an all 0s sequence indicates the maximum negative amplitude. Anequal number of 1s and 0s indicates a zero amplitude. Other values between the positive and negativemaxima are indicated by a proportional number of 1s relative to the number of 0s. This is furtherillustrated in Fig. 12.40.