Digital Electronics: Principles, Devices and Applications

236 Digital Electronicsof Boolean expressions. The following guidelines should be followed while choosing the preferredform for hardware implementation:1. The implementation should have the minimum number of gates, with the gates used having theminimum number of inputs.2. There should be a minimum number of interconnections, and the propagation time should be theshortest.3. Limitation on the driving capability of the gates should not be ignored.It is difficult to generalize as to what constitutes an acceptable simplified Boolean expression. Theimportance of each of the above-mentioned aspects is governed by the nature of application.7.3 Arithmetic Circuits – Basic Building BlocksIn this section, we will discuss those combinational logic building blocks that can be used to performaddition and subtraction operations on binary numbers. Addition and subtraction are the two mostcommonly used arithmetic operations, as the other two, namely multiplication and division, arerespectively the processes of repeated addition and repeated subtraction, as was outlined in Chapter2 dealing with binary arithmetic. We will begin with the basic building blocks that form the basis ofall hardware used to perform the aforesaid arithmetic operations on binary numbers. These includehalf-adder, full adder, half-subtractor, full subtractor and controlled inverter.7.3.1 Half-AdderA half-adder is an arithmetic circuit block that can be used to add two bits. Such a circuit thus has twoinputs that represent the two bits to be added and two outputs, with one producing the SUM outputand the other producing the CARRY. Figure 7.4 shows the truth table of a half-adder, showing allpossible input combinations and the corresponding outputs.The Boolean expressions for the SUM and CARRY outputs are given by the equationsSUM S = AB + AB (7.5)CARRY C = AB (7.6)An examination of the two expressions tells that there is no scope for further simplification. Whilethe first one representing the SUM output is that of an EX-OR gate, the second one representing theFigure 7.4Truth table of a half-adder.