Digital Electronics: Principles, Devices and Applications

0616 Digital ElectronicsData InputR/WCSInput Buffers01AddressLinesRowDecoderMemory array128 rows ×128 columns ×8 bitsOutputBuffersDataOutput1281 128Column DecoderAddressLinesFigure 15.7Typical architecture of a 16K×8 asynchronous SRAM.• Complete write cycle time t WC . This is defined as the time interval for which a valid address codeis applied to the address lines during the ‘write’ operation.• Write pulse width t W . This is the time for which R/W is held LOW during the ‘write’ operation.• Address set-up time t AS .This is the time interval between the appearance of a new address and R/Wgoing LOW.• Data set-up time t DS . This is defined as the time interval for which the R/W must remain LOWafter valid data are applied to the data inputs.• Data hold time t DH . This is defined as the time interval for which valid input data must remain onthe data lines after the R/W input goes HIGH.• Address hold time interval t AH . This is defined as the time interval for which the valid address mustremain on the address lines after the R/W input goes HIGH.15.5.1.2 Synchronous SRAMSynchronous SRAM, as mentioned before, is synchronized with the system clock. In the case of acomputer system it operates at the same clock frequency as the microprocessor. This synchronizationof microprocessor and memory ensures faster execution speeds. The basic difference between thearchitecture of synchronous and asynchronous SRAMs is that the synchronous SRAM makes use ofclocked registers to synchronize ‘address’, R/W , CS and ‘data in’ lines to the system clock. Figure15.9 shows the basic architecture of a 32K × 8 synchronous SRAM with a burst feature. As we cansee from the figure, the memory array block, the address decoder block and R/W and CS are the same