Digital Electronics: Principles, Devices and Applications

304 Digital ElectronicsD C B AProgrammable OR-arrayProgrammable AND-arrayY1Y2Figure 9.4Internal architecture of a PLA device.is usually much less than 2 m , and the number of inputs of each of the OR gates equals the number ofAND gates. Each OR gate can generate an arbitrary Boolean function with a maximum of mintermsequal to the number of AND gates. Figure 9.4 shows the internal architecture of a PLA device withfour input lines, a programmable array of eight AND gates at the input and a programmable array oftwo OR gates at the output. A PLA device makes more efficient use of logic capacity than a PROM.However, it has its own disadvantages resulting from two sets of programmable fuses, which makes itrelatively more difficult to manufacture, program and test.9.2.3 Programmable Array LogicProgrammable array logic (PAL) architecture has a programmable AND array at the input and a fixedOR array at the output. The programmable AND array of a PAL device is similar to that of a PLAdevice. That is, the number of programmable AND gates is usually smaller than the number required