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Encyclopedia of Computer Science and Technology

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multiprocessing 323music <strong>and</strong> video players, digital; smartphones; <strong>and</strong> digitalconvergence). Further, equipped with digital cameras<strong>and</strong> camcorders (even cell-phone cameras), togetherwith easy-to-use editing s<strong>of</strong>tware, more <strong>and</strong> more peopleare becoming not just consumers <strong>of</strong> multimedia, but creatorsas well (see user-created content <strong>and</strong> YouTube).Further ReadingCoorough, Calleen, <strong>and</strong> James E. Shuman. Multimedia for the Web:Creating Digital Excitement. Boston: Thomson Course <strong>Technology</strong>,2005.Lauer, David, <strong>and</strong> Stephen Pentak. Design Basics: Multimedia Edition.6th ed. Belmont, Calif.: Wadsworth Publishing, 2006.MIT Media Lab. Available online. URL: http://www.media.mit.edu.Accessed August 15, 2007.“Multimedia <strong>and</strong> Authoring Resources on the Internet.” NorthwesternUniversity Library. Available online. URL: http://www.library.northwestern.edu/dms/multimedia.html.Accessed August 15, 2007.Packer, R<strong>and</strong>all, <strong>and</strong> Ken Jordan. Multimedia: From Wagner to VirtualReality. Exp<strong>and</strong>ed ed. New York: Norton, 2002.Vaughan, Tay. Multimedia: Making It Work. 7th ed. New York:McGraw-Hill/Osborne Media, 2006.multiprocessingOne way to increase the power <strong>of</strong> a computer is to use morethan one processing unit. In early computers (see mainframe)a single processor h<strong>and</strong>led both program execution<strong>and</strong> input/output (I/O) operations. In the late 1950s,however, machines such as the IBM 709 introduced theconcept <strong>of</strong> channels, or separate processing units for I/Ooperations. In such systems the central processor sends aset <strong>of</strong> I/O comm<strong>and</strong>s (such as to read a file into memory) tothe channel, which has its own processor for carrying outthe operation.True multiprocessing, however, involves the use <strong>of</strong> morethan one central processing unit (CPU). One successfuldesign, Control Data Corporation’s CDC 6600 (1964), containedboth multiple arithmetic/logic units (the part <strong>of</strong> theCPU that does calculations) <strong>and</strong> multiple controllers for I/O<strong>and</strong> memory access control. IBM soon added multiprocessingcapability to its 360 line <strong>of</strong> mainframes.Multiprocessing can be either asymmetric or symmetric.Asymmetric multiprocessing essentially maintains a singlemain flow <strong>of</strong> execution with certain tasks being “h<strong>and</strong>edover” by the CPU to auxiliary processors. (For example,the Intel 80386 processor could be purchased with an additionalfloating-point processor, allowing such calculationsto be performed using more efficient hardware. When thePentium line was developed, floating-point was integratedinto the main CPU).Symmetric multiprocessing (SMP) has multiple, fullfledgedCPUs, each capable <strong>of</strong> the full range <strong>of</strong> operations.The processors share the same memory space, whichrequires that each processor that accesses a given memorylocation be able to retrieve the same value. This coherence<strong>of</strong> memory is threatened if one processor is in the midst<strong>of</strong> a memory access while another is trying to write datato that same memory location. This is usually h<strong>and</strong>led bya “locking” mechanism (see concurrent programming)that prevents two processors from simultaneously accessingthe same location.A subtler problem occurs with the use by processors <strong>of</strong>separate internal memory for storing data that is likely tobe needed (see cache). Suppose CPU “A” reads some datafrom memory <strong>and</strong> stores it in its cache. A moment later,CPU “B” writes to that memory location, changing the data.At this point the data in “A’s” cache no longer matches thatin the actual memory. One way to deal with this problemis called bus snooping. Each CPU includes a controller thatmonitors the data line (see bus) for memory locations beingused by other CPUs. When it sees an address that refers toan area <strong>of</strong> memory currently being stored in the cache, thecontroller updates the memory from the cache. This writeoperation sends a signal that lets other CPUs know that anycached data they have for that location is no longer valid.This means the other CPUs will go back to memory <strong>and</strong>reread the current data.Alternatively, all CPUs can be given a single sharedcache. While less complicated, this approach limits thenumber <strong>of</strong> CPUs to the maximum data-h<strong>and</strong>ling capacity<strong>of</strong> the bus.Larger-scale multiprocessing systems consist <strong>of</strong> latticelikearrays <strong>of</strong> hundreds or even thous<strong>and</strong>s <strong>of</strong> CPUs,which are referred to as nodes. Indeed, small clusters <strong>of</strong>CPUs using the architecture given above can be connectedtogether to form larger arrays. Each cluster can have itsown shared memory cache. Because accessing memory ata remote node takes considerably longer than accessingThis example shows what can happen if processes do not properlymanage a shared memory resource. At (1) processor A retrieves3 from the memory location. At (2) processor B copies 7 from itscache to that same memory location. Finally, at (3) processor Aadds the 3 it had retrieved to a 2 in its register, storing 5 back in alocation where processor B probably expects there to still be a 7.

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