TMS320C6713B Floating-Point Digital Signal Processor (Rev. A)

SPRS294 − OCTOBER 2005
electrical characteristics over recommended ranges of supply voltage and operating case
temperature † (unless otherwise noted)
VOH
VOL
II
IOZ
IDD2V
IDD3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-level output All signals except SCL1, SDA1,
voltage
SCL0, and SDA0
IOH =MAX 2.4 V
Low-level output
voltage
Input current
Off-state output
current
Core supply current‡
I/O supply current‡
All signals except SCL1, SDA1,
SCL0, and SDA0
IOL = MAX 0.4 V
SCL1, SDA1, SCL0, and SDA0 IOL = MAX 0.4 V
All signals except SCL1, SDA1,
SCL0, and SDA0
SCL1, SDA1, SCL0, and SDA0
All signals except SCL1, SDA1,
SCL0, and SDA0
SCL1, SDA1, SCL0, and SDA0
VI = VSS to DVDD
VO = DVDD or 0 V
GDP/ZDP, CVDD = 1.4 V,
CPU clock = 300 MHz
GDP/ZDP/PYP, CVDD =
1.26 V, CPU clock = 225
MHz
GDPA/ZDPA, CVDD =1.26V
CPU clock = 200 MHz
GDPA/ZDPA/PYP/ PYPA
CVDD =1.2 V CPU clock =
200 MHz
PYPA, CVDD =1.2 V CPU
clock = 167 MHz
DVDD = 3.3 V, EMIF speed
= 100 MHz
±170 uA
±10 uA
±170 uA
±10 uA
945 mA
625 mA
560 mA
565 mA
480 mA
75 mA
Ci Input capacitance 7 pF
Co Output capacitance 7 pF
† For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
‡ Measured with average activity (50% high/50% low power) at 25°C case temperature and 100-MHz EMIF. This model represents a device
performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The high/low-DSP-activity
models are defined as follows:
High-DSP-Activity Model:
CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;
L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
Low-DSP-Activity Model:
CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;
L2/EMIF EDMA: None]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6711D, C6712D, C6713B
Power Consumption Summary application report (literature number SPRA889A2 or later).
100 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443